Cortex-M3 Technical Reference Manual: 7.2.2. AHB-AP programmers model

7.2.2. AHB-AP programmers model

Table 7.5 shows the AHB-AP registers. If the AHB-AP is not present, these registers read as zero. Any register that is not specified in this table reads as zero.

Table 7.5. AHB-AP register summary

Offset^[a]	Name	Type	Reset	Description
`0x00`	CSW	RW	See register	AHB-AP Control and Status Word Register, CSW
`0x04`	TAR	RW	-	AHB-AP Transfer Address Register
`0x0C`	DRW	RW	`-`	AHB-AP Data Read/Write Register
`0x10`	BD0	RW	-	AHB-AP Banked Data Register0
`0x14`	BD1	RW	-	AHB-AP Banked Data Register1
`0x18`	BD2	RW	-	AHB-AP Banked Data Register2
`0x1C`	BD3	RW	-	AHB-AP Banked Data Register3
`0xF8`	DBGDRAR	RO	`0xE00FF003`	AHB-AP ROM Address Register
`0xFC`	IDR	RO	`0x24770011`	AHB-AP Identification Register
^[a]The offset given in this table is relative to the location of the AHB-AP in the DAP memory space. This space is only visible from the access port. It is not part of the processor memory map.

The following sections describe the AHB-AP registers whose implementation is specific to this processor. Other registers are described in the CoreSight Components Technical Reference Manual.

AHB-AP Control and Status Word Register, CSW

The CSW characteristics are:

Purpose: Configures and controls transfers through the AHB interface.
Usage constraints: There are no usage constraints.
Configurations: This register is available in all processor configurations.
Attributes: See the register summary in Table 7.5.

Figure 7.2 shows the CSW bit assignments.

Figure 7.2. CSW bit assignments

Table 7.6 shows the CSW bit assignments.

Table 7.6. CSW bit assignments

Bits	Name	Function
[31:30]	-	Reserved. Read as 0b00.
[29]	MasterType^[a]	0 = core. 1 = debug. This bit must not be changed if a transaction is outstanding. A debugger must first check bit [7], TransInProg. Reset value = 0b1. An implementation can configure this bit to be read only with a value of 1. In that case, transactions are always indicated as debug.
[28:26]	-	Reserved, 0b000.
[25]	Hprot1	User and Privilege control - HPROT[1]. Reset value = 0b1.
[24]	-	Reserved, 0b1.
[23:12]	-	Reserved, `0x000`.
[11:8]	Mode	Mode of operation bits: b0000 = normal download and upload mode b0001-b1111 are reserved. Reset value = 0b0000.
[7]	TransInProg	Transfer in progress. This field indicates if a transfer is in progress on the APB master port.
[6]	DbgStatus	Indicates the status of the DAPEN port. 1 = AHB transfers permitted. 0 = AHB transfers not permitted.
[5:4]	AddrInc	Auto address increment and pack mode on Read or Write data access. Only increments if the current transaction completes with no error. Auto address incrementing and packed transfers are not performed on access to Banked Data registers `0x10 - 0x1C`. The status of these bits is ignored in these cases. Increments and wraps within a 4-KB address boundary, for example from `0x1000 to 0x1FFC`. If the start is at `0x14A0`, then the counter increments to `0x1FFC`, wraps to `0x1000`, then continues incrementing to `0x149C`. 0b00 = auto increment off. 0b01 = increment single. Single transfer from corresponding byte lane. 0b10 = increment packed.^[b] 0b11 = reserved. No transfer. Size of address increment is defined by the Size field [2:0]. Reset value: 0b00.
[3]	-	Reserved.
[2:0]	Size	Size of access field: b000 = 8 bits b001 = 16 bits b010 = 32 bits b011-111 are reserved. Reset value: b000.
^[a]When clear, this bit prevents the debugger from setting the C_DEBUGEN bit in the Debug Halting Control and Status Register, and so prevents the debugger from being able to halt the processor. ^[b]See the definition of packed transfers in the ARM Debug Interface v5 Architecture Specification.

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