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The ETMCCER characteristics are:
Holds ETM configuration information additional to that in the ETMCCR. See Configuration Code Register, ETMCCR.
There are no usage constraints.
This register is only available if the processor is configured to use the ETM.
See the register summary in Table 10.6.
Figure 10.7 shows the ETMCCER bit assignments.
Table 10.12 shows the ETMCCER bit assignments.
Table 10.12. ETMCCER bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:22] | - | Reserved. Read-As-Zero. |
| [21] | EmbeddedICE behavior control implemented | The value of this bit is 0, indicating that the ETMEIBCR is not implemented. For more information on EmbeddedICE behavior see the Embedded Trace Macrocell Architecture Specification. |
| [20] | Trace Start/Stop block uses EmbeddedICE watchpoint inputs | The value of this bit is 1, indicating that the Trace Start/Stop block uses the EmbeddedICE watchpoint inputs. |
| [19:16] | EmbeddedICE watchpoint inputs | The value of these bits is b0100, indicating that the number of EmbeddedICE watchpoint inputs implemented is four. These inputs come from the DWT. |
| [15:13] | Instrumentation resources | The value of these bits is b000, indicating that no Instrumentation resources are supported. |
| [12] | Data address comparisons | The value of this bit is 1, indicating that data address comparisons are not supported. |
| [11] | Readable registers | The value of this bit is 1, indicating that all registers are readable. |
| [10:3] | Extended external input bus | The value of these bits is 0, indicating that the extended external input bus is not implemented. |
| [2:0] | Extended external input selectors | The value of these bits is 0, indicating that extended external input selectors are not implemented. |
| Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. | ARM DDI 0337H |
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| Home > Embedded Trace Macrocell > ETM Programmers model > Configuration Code Extension Register, ETMCCER |