Cortex™-M3 Technical Reference Manual

Revision r2p0

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on this manual
1. Introduction
1.1. About the processor
1.2. Features
1.3. Interfaces
1.4. Configurable options
1.5. Product documentation
1.5.1. Documentation
1.5.2. Design Flow
1.5.3. Architecture and protocol information
1.6. Product revisions
1.6.1. Differences in functionality between r0p0 and r1p0
1.6.2. Differences in functionality between r1p0 and r1p1
1.6.3. Differences in functionality between r1p1 and r2p0
2. Functional Description
2.1. About the functions
2.2. Interfaces
2.2.1. Bus interfaces
2.2.2. ETM interface
2.2.3. AHB Trace Macrocell interface
2.2.4. Debug port AHB-AP interface
3. Programmers Model
3.1. About the programmers model
3.2. Modes of operation and execution
3.2.1. Operating modes
3.2.2. Operating states
3.2.3. Privileged access and user access
3.3. Instruction set summary
3.3.1. Cortex-M3 instructions
3.3.2. Load/store timings
3.3.3. Binary compatibility with other Cortex processors
3.4. System address map
3.4.1. Private peripheral bus
3.4.2. Unaligned accesses that cross regions
3.5. Write buffer
3.6. Exclusive monitor
3.7. Bit-banding
3.7.1. Directly accessing an alias region
3.7.2. Directly accessing a bit-band region
3.8. Processor core register summary
3.9. Exceptions
3.9.1. Exception handling
4. System Control
4.1. About system control
4.2. Register summary
4.3. Register descriptions
4.3.1. Auxiliary Control Register, ACTLR
4.3.2. CPUID Base Register, CPUID
4.3.3. Auxiliary Fault Status Register, AFSR
5. Memory Protection Unit
5.1. About the MPU
5.2. MPU functional description
5.3. MPU programmers model
6. Nested Vectored Interrupt Controller
6.1. About the NVIC
6.2. NVIC functional description
6.2.1. Low power modes
6.2.2. Level versus pulse interrupts
6.3. NVIC programmers model
6.3.1. Interrupt Controller Type Register, ICTR
7. Debug
7.1. About debug
7.1.1. Cortex-M3 ROM table identification and entries
7.1.2. System Control Space
7.1.3. Debug register summary
7.2. About the AHB-AP
7.2.1. AHB-AP transaction types
7.2.2. AHB-AP programmers model
7.3. About the Flash Patch and Breakpoint Unit (FPB)
7.3.1. FPB functional description
7.3.2. FPB programmers model
8. Data Watchpoint and Trace Unit
8.1. About the DWT
8.2. DWT functional description
8.3. DWT Programmers Model
9. Instrumentation Trace Macrocell Unit
9.1. About the ITM
9.2. ITM functional description
9.3. ITM programmers model
9.3.1. ITM Trace Privilege Register, ITM_TPR
10. Embedded Trace Macrocell
10.1. About the ETM
10.1.1. Features
10.1.2. Configurable options
10.2. ETM functional description
10.2.1. Resources
10.2.2. Periodic synchronization
10.2.3. Data and instruction address compare resources
10.2.4. External inputs
10.2.5. Start/stop block
10.2.6. Triggering
10.2.7. Interfaces
10.2.8. Operation
10.3. ETM Programmers model
10.3.1. Modes of operation and execution
10.3.2. Register summary
10.3.3. Main Control Register, ETMCR
10.3.4. Configuration Code Register, ETMCCR
10.3.5. System Configuration Register, ETMSCR
10.3.6. TraceEnable Control 1 Register, ETMTECR1
10.3.7. ID Register, ETMIDR
10.3.8. Configuration Code Extension Register, ETMCCER
10.3.9. TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
10.3.10. Device Power-Down Status Register, ETMPDSR
10.3.11. Integration Test Miscellaneous Inputs, ITMISCIN
10.3.12. Integration Test Trigger Out, ITTRIGOUT
10.3.13. ETM Integration Test ATB Control 2, ETM_ITATBCTR2
10.3.14. ETM Integration Test ATB Control 0, ETM_ITATBCTR0
11. Trace Port Interface Unit
11.1. About the Cortex-M3 TPIU
11.2. TPIU functional description
11.2.1. TPIU block diagrams
11.2.2. TPIU Formatter
11.2.3. Serial Wire Output format
11.3. TPIU programmers model
11.3.1. Asynchronous Clock Prescaler Register, TPIU_ACPR
11.3.2. Formatter and Flush Status Register, TPIU_FFSR
11.3.3. Formatter and Flush Control Register, TPIU_FFCR
11.3.4. TRIGGER
11.3.5. Integration FIFO 0 Data
11.3.6. ITATBCTR2
11.3.7. Integration FIFO 1 Data
11.3.8. ITATBCTR0
11.3.9. Integration Mode Control, TPIU_ITCTRL
11.3.10. TPIU_DEVID
A. Revisions

List of Tables

3.1. Cortex-M3 instruction set summary
3.2. Memory regions
4.1. System control registers
4.2. ACTLR bit assignments
4.3. CPUID bit assignments
4.4. AFSR bit assignments
5.1. MPU registers
6.1. NVIC registers
6.2. ICTR bit assignments
7.1. Cortex-M3 ROM table identification values
7.2. Cortex-M3 ROM table components
7.3. SCS identification values
7.4. Debug registers
7.5. AHB-AP register summary
7.6. CSW bit assignments
7.7. FPB register summary
8.1. DWT register summary
9.1. ITM register summary
9.2. ITM_TPR bit assignments
10.1. Cortex-M3 resources
10.2. Boolean function encoding for events
10.3. Resource identification encoding
10.4. Input connections
10.5. Trigger output connections
10.6. ETM registers
10.7. ETMCR bit assignments
10.8. ETMCCR bit assignments
10.9. ETMSCR bit assignments
10.10. ETMTECR1 bit assignments
10.11. ETMIDR bit assignments
10.12. ETMCCER bit assignments
10.13. ETMTESSEICR bit assignments
10.14. ETMPDSR bit assignments
10.15. ITMISCIN bit assignments
10.16. ITTRIGOUT bit assignments
10.17. ETM_ITATBCTR2 bit assignments
10.18. ETM_ITATBCTR0 bit assignments
11.1. TPIU registers
11.2. TPIU_ACPR bit assignments
11.3. TPIU_FFSR bit assignments
11.4. TPIU_FFCR bit assignments
11.5. TRIGGER bit assignments
11.6. Integration FIFO 0 bit assignments
11.7. ITATBCTR2 bit assignments
11.8. Integration FIFO 1 Data bit assignments
11.9. ITATBCTR0 bit assignments
11.10. TPIU_ITCTRL bit assignments
11.11. TPIU_DEVID bit assignments
A.1. Differences between issue E and issue F
A.2. Differences between issue F and issue G
A.3. Differences between issue G and issue H

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Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Unrestricted Access is an ARM internal classification.

Product Status

The information in this document is Final (information on a developed product).

Revision History
Revision A15 December 2005First Release
Revision B13 January 2006Confidentiality status amended
Revision C10 May 2006First Release for r1p0
Revision D27 September 2006First Release for r1p1
Revision E13 June 2007Minor update with no technical changes
Revision F11 April 2008Limited release for SC300 r0p0
Revision G26 June 2008First Release for r2p0
Revision H26 February 2010Second Release for r2p0
Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.ARM DDI 0337H