11.3. TPIU programmers model

Table 11.1 provides a summary of the TPIU registers. Depending on the implementation of your processor, the TPIU registers might not be present, or the CoreSight TPIU might be present instead. Any register that is configured as not present reads as zero.

Table 11.1. TPIU registers

AddressNameTypeReset Description
0xE0040000TPIU_SSPSRRO0x0xx Supported Parallel Port Size Register
0xE0040004TPIU_CSPSRRW0x01Current Parallel Port Size Register
0xE0040010TPIU_ACPRRW0x0000Asynchronous Clock Prescaler Register, TPIU_ACPR
0xE00400F0TPIU_SPPRRW0x01Selected Pin Protocol Register
0xE0040300TPIU_FFSRRO0x08Formatter and Flush Status Register, TPIU_FFSR
0xE0040304TPIU_FFCRRW0x102Formatter and Flush Control Register, TPIU_FFCR
0xE0040308TPIU_FSCRRO0x00Formatter Synchronization Counter Register
0xE0040EE8 TRIGGERRO0x0TRIGGER
0xE0040EEC FIFO data 0 RO0x--000000 Integration ETM Data
0xE0040EF0 ITATBCTR2 RO0x0 ITATBCTR2
0xE0040EFC FIFO data 1RO0x--000000 Integration ITM Data
0xE0040EF8 ITATBCTR0 RO0x0ITATBCTR0
0xE0040F00 ITCTRLRW0x0Integration Mode Control, TPIU_ITCTRL
0xE0040FA0 CLAIMSETRW0xF Claim tag set
0xE0040FA4 CLAIMCLRRW0x0 Claim tag clear
0xE0040FC8 DEVIDRO0xCA0/0xCA1TPIU_DEVID
0xE0040FCC DEVTYPERO0x11TPIU_DEVTYPE
0xE0040FD0PID4RO0x04Peripheral identification registers
0xE0040FD4PID5RO0x00
0xE0040FD8PID6RO0x00
0xE0040FDCPID7RO0x00
0xE0040FE0PID0RO0x23
0xE0040FE4PID1RO0xB9
0xE0040FE8PID2RO0x3B
0xE0040FECPID3RO0x00
0xE0040FF0CID0RO0x0DComponent identification registers
0xE0040FF4CID1RO0x90
0xE0040FF8CID2RO0x05
0xE0040FFCCID3RO0xB1

The following sections describe the TPIU registers whose implementation is specific to this processor. The Formatter, Integration Mode Control, and Claim Tag registers are described in the CoreSight Components Technical Reference Manual. Other registers are described in the ARMv7-M Architecture Reference Manual.

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