Cortex-M3 Technical Reference Manual: 4.2. Register summary

4.2. Register summary

Table 4.1 shows the system control registers. Registers not described in this chapter are described in the ARMv7-M Architecture Reference Manual

Table 4.1. System control registers

Address	Name	Type	Reset	Description
`0xE000E008`	ACTLR	RW	`0x00000000`	Auxiliary Control Register, ACTLR
`0xE000E010`	STCSR	RW	`0x00000000`	SysTick Control and Status Register
`0xE000E014`	STRVR	RW	Unknown	SysTick Reload Value Register
`0xE000E018`	STCVR	RW clear	Unknown	SysTick Current Value Register
`0xE000E01C`	STCR	RO	Implementation specific	SysTick Calibration Value Register
`0xE000ED00`	CPUID	RO	`0x412FC231`	CPUID Base Register, CPUID
`0xE000ED04`	ICSR	RW or RO	`0x00000000`	Interrupt Control and State Register
`0xE000ED08`	VTOR	RW	`0x00000000`	Vector Table Offset Register
`0xE000ED0C`	AIRCR	RW	`0x00000000`^[a]	Application Interrupt and Reset Control Register
`0xE000ED10`	SCR	RW	`0x00000000`	System Control Register
`0xE000ED14`	CCR	RW	`0x00000200`	Configuration and Control Register.
`0xE000ED18`	SHPR1	RW	`0x00000000`	System Handler Priority Register 1
`0xE000ED1C`	SHPR2	RW	`0x00000000`	System Handler Priority Register 2
`0xE000ED20`	SHPR3	RW	`0x00000000`	System Handler Priority Register 3
`0xE000ED24`	SHCSR	RW	`0x00000000`	System Handler Control and State Register
`0xE000ED28`	CFSR	RW	`0x00000000`	Configurable Fault Status Registers
`0xE000ED2C`	HFSR	RW	`0x00000000`	HardFault Status Register
`0xE000ED30`	DFSR	RW	`0x00000000`	Debug Fault Status Register
`0xE000ED34`	MMFAR	RW	Unknown	MemManage Fault Address Register^[b]
`0xE000ED38`	BFAR	RW	Unknown	BusFault Address Register^[b]
`0xE000ED3C`	AFSR	RW	`0x00000000`	Auxiliary Fault Status Register, AFSR
`0xE000ED40`	ID_PFR0	RO	`0x00000030`	Processor Feature Register 0
`0xE000ED44`	ID_PFR1	RO	`0x00000200`	Processor Feature Register 1
`0xE000ED48`	ID_DFR0	RO	`0x00100000`	Debug Features Register 0^[c]
`0xE000ED4C`	ID_AFR0	RO	`0x00000000`	Auxiliary Features Register 0
`0xE000ED50`	ID_MMFR0	RO	`0x00100030`	Memory Model Feature Register 0
`0xE000ED54`	ID_ MMFR1	RO	`0x00000000`	Memory Model Feature Register 1
`0xE000ED58`	ID_MMFR2	RO	`0x01000000`	Memory Model Feature Register 2
`0xE000ED5C`	ID_MMFR3	RO	`0x00000000`	Memory Model Feature Register 3
`0xE000ED60`	ID_ISAR0	RO	`0x01100110`	Instruction Set Attributes Register 0
`0xE000ED64`	ID_ISAR1	RO	`0x02111000`	Instruction Set Attributes Register 1
`0xE000ED68`	ID_ISAR2	RO	`0x21112231`	Instruction Set Attributes Register 2
`0xE000ED6C`	ID_ISAR3	RO	`0x01111110`	Instruction Set Attributes Register 3
`0xE000ED70`	ID_ISAR4	RO	`0x01310132`	Instruction Set Attributes Register 4
`0xE000ED88`	CPACR	RW	`0x00000000`	Coprocessor Access Control Register
`0xE000EF00`	STIR	WO	`0x00000000`	Software Triggered Interrupt Register
^[a]Bits [10:8] are reset to zero. The ENDIANNESS bit, bit [15], can reset to either state, depending on the implementation. ^[b]BFAR and MMFAR are the same physical register. Because of this, the BFARVALID and MMFARVALID bits are mutually exclusive. ^[c]ID_DFR0 will read as 0 if no debug support is implemented.

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