4.2. Register summary

Table 4.1 shows the system control registers. Registers not described in this chapter are described in the ARMv7-M Architecture Reference Manual

Table 4.1. System control registers

AddressNameTypeResetDescription
0xE000E008ACTLRRW0x00000000Auxiliary Control Register, ACTLR
0xE000E010STCSRRW0x00000000SysTick Control and Status Register
0xE000E014STRVRRWUnknownSysTick Reload Value Register
0xE000E018STCVRRW clearUnknownSysTick Current Value Register
0xE000E01CSTCRROImplementation specificSysTick Calibration Value Register
0xE000ED00CPUIDRO0x412FC231CPUID Base Register, CPUID
0xE000ED04ICSRRW or RO0x00000000Interrupt Control and State Register
0xE000ED08VTORRW0x00000000Vector Table Offset Register
0xE000ED0CAIRCRRW0x00000000[a]Application Interrupt and Reset Control Register
0xE000ED10SCRRW0x00000000System Control Register
0xE000ED14CCRRW0x00000200Configuration and Control Register.
0xE000ED18SHPR1RW0x00000000System Handler Priority Register 1
0xE000ED1CSHPR2RW0x00000000System Handler Priority Register 2
0xE000ED20SHPR3RW0x00000000System Handler Priority Register 3
0xE000ED24SHCSRRW0x00000000System Handler Control and State Register
0xE000ED28CFSRRW0x00000000Configurable Fault Status Registers
0xE000ED2CHFSRRW0x00000000HardFault Status Register
0xE000ED30DFSRRW0x00000000Debug Fault Status Register
0xE000ED34MMFARRWUnknownMemManage Fault Address Register[b]
0xE000ED38BFARRWUnknownBusFault Address Register[b]
0xE000ED3CAFSRRW0x00000000Auxiliary Fault Status Register, AFSR
0xE000ED40ID_PFR0RO0x00000030Processor Feature Register 0
0xE000ED44ID_PFR1RO0x00000200Processor Feature Register 1
0xE000ED48ID_DFR0RO0x00100000Debug Features Register 0[c]
0xE000ED4CID_AFR0RO0x00000000Auxiliary Features Register 0
0xE000ED50ID_MMFR0RO0x00100030Memory Model Feature Register 0
0xE000ED54ID_ MMFR1RO0x00000000Memory Model Feature Register 1
0xE000ED58ID_MMFR2RO0x01000000Memory Model Feature Register 2
0xE000ED5CID_MMFR3RO0x00000000Memory Model Feature Register 3
0xE000ED60ID_ISAR0RO0x01100110Instruction Set Attributes Register 0
0xE000ED64ID_ISAR1RO0x02111000Instruction Set Attributes Register 1
0xE000ED68ID_ISAR2RO0x21112231Instruction Set Attributes Register 2
0xE000ED6CID_ISAR3RO0x01111110Instruction Set Attributes Register 3
0xE000ED70ID_ISAR4RO0x01310132Instruction Set Attributes Register 4
0xE000ED88CPACRRW0x00000000Coprocessor Access Control Register
0xE000EF00STIRWO0x00000000Software Triggered Interrupt Register

[a] Bits [10:8] are reset to zero. The ENDIANNESS bit, bit [15], can reset to either state, depending on the implementation.

[b] BFAR and MMFAR are the same physical register. Because of this, the BFARVALID and MMFARVALID bits are mutually exclusive.

[c] ID_DFR0 will read as 0 if no debug support is implemented.


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