Cortex-M3 Technical Reference Manual Revision r2p1
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1.4. Configurable options

You can configure your Cortex-M3 implementation to include the following optional components:

Table 1.1. Optional implementation components

ComponentDescription
MPUSee Chapter 5 Memory Protection Unit
FPBFlash Patch and Breakpoint Unit. See Chapter 7 Debug
DWTSee Chapter 8 Data Watchpoint and Trace Unit
ITMSee Chapter 9 Instrumentation Trace Macrocell Unit
ETMSee Chapter 10 Embedded Trace Macrocell
AHB-APAdvanced High-performance Bus Access Port. See Chapter 7 Debug
HTM interfaceSee AHB Trace Macrocell interface
TPIUSee Chapter 11 Trace Port Interface Unit
WICWake-up Interrupt Controller. See Low power modes
Debug PortSee Debug Port AHB-AP interface
Constant AHB controlSee Bus interfaces

Note

You can only configure trace functionality in the following combinations:

  • no trace functionality

  • ITM and DWT

  • ITM, DWT, and ETM

  • ITM, DWT, ETM, and HTM.

You can configure the debug features provided in the DWT independently.

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