7.3.1. FPB functional description

The FPB contains both a global enable and individual enables for the eight comparators. If the comparison for an entry matches, the address is either:

The comparison happens dynamically, but the result of the comparison occurs too late to stop the original instruction fetch or literal load taking place from the Code space. The processor ignores this transaction however, and only the remapped transaction is used.

If an MPU is present, the MPU lookups are performed for the original address, not the remapped address.

You can remove the FPB if no debug is required, or you can reduce the number of breakpoints it supports to two. If the FPB supports only two breakpoints then only comparators 0 and 1 are used, and the FPB does not support flash patching.

Note

  • Unaligned literal accesses are not remapped. The original access to the DCode bus takes place in this case.

  • Load exclusive accesses can be remapped. However, it is Unpredictable whether they are performed as exclusive accesses or not.

  • Setting the flash patch remap location to a bit-band alias is not supported and results in Unpredictable behavior.

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