7.1.3. Debug register summary

Table 7.4 shows the debug registers. Each of these registers is 32 bits wide and is described in the ARMv7-M Architectural Reference Manual.

Table 7.4. Debug registers

AddressNameTypeResetDescription
0xE000ED30DFSRRW0x00000000[a]Debug Fault Status Register
0xE000EDF0DHCSRRW0x00000000Debug Halting Control and Status Register
0xE000EDF4DCRSRWO-Debug Core Register Selector Register
0xE000EDF8DCRDRRW-Debug Core Register Data Register
0xE000EDFCDEMCRRW0x00000000Debug Exception and Monitor Control Register

[a] Power-on reset only


Core debug is an optional component. If core debug is removed then halt mode debugging is not supported, and there is no halt, stepping, or register transfer functionality. Debug monitor mode is still supported.

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