7.1.3. Debug register summary
Table 7.4 shows
the debug registers. Each of these registers is 32 bits wide and
is described in the ARMv7-M Architectural Reference Manual.
Table 7.4. Debug registers
| Address | Name | Type | Reset | Description |
|---|
0xE000ED30 | DFSR | RW | 0x00000000[] | Debug Fault Status Register |
0xE000EDF0 | DHCSR | RW | 0x00000000 | Debug Halting Control and Status Register |
0xE000EDF4 | DCRSR | WO | - | Debug Core Register Selector Register |
0xE000EDF8 | DCRDR | RW | - | Debug Core Register Data Register |
0xE000EDFC | DEMCR | RW | 0x00000000 | Debug Exception and Monitor Control Register |
Core debug is an optional component. If core debug is removed
then halt mode debugging is not supported, and there is no halt,
stepping, or register transfer functionality. Debug monitor mode is
still supported.
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