7.1.2. System Control Space

If debug is implemented, the processor provides debug through registers in the SCS. See:

SCS CoreSight identification

Table 7.3 shows the SCS CoreSight identification registers and values for debugger detection. Final debugger identification of the Cortex-M3 processor is through the CPUID register in the SCS. See CPUID Base Register, CPUID.

Table 7.3. SCS identification values

AddressRegisterValueDescription
0xE000EFD0 Peripheral ID40x00000004Component and Peripheral ID register formats in the ARMv7-M Architectural Reference Manual.
0xE000EFE0Peripheral ID00x00000000
0xE000EFE4Peripheral ID10x000000B0
0xE000EFE8Peripheral ID20x0000000B
0xE000EFECPeripheral ID30x00000000
0xE000EFF0Component ID00x0000000D
0xE000EFF4Component ID10x000000E0
0xE000EFF8Component ID20x00000005
0xE000EFFCComponent ID30x000000B1

See the ARMv7-M Architectural Reference Manual and the ARM CoreSight Components Technical Reference Manual for more information about the SCS CoreSight identification registers, and their addresses and access types.

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