If debug is implemented, the processor provides debug through
registers in the SCS. See:
SCS CoreSight identification
Table 7.3 shows
the SCS CoreSight identification registers and values for debugger
detection. Final debugger identification of the Cortex-M3 processor
is through the CPUID register in the SCS. See CPUID Base Register, CPUID.
Table 7.3. SCS identification values
| Address | Register | Value | Description |
|---|
0xE000EFD0 | Peripheral ID4 | 0x00000004 | Component and Peripheral
ID register formats in the ARMv7-M Architectural
Reference Manual. |
0xE000EFE0 | Peripheral ID0 | 0x00000000 |
0xE000EFE4 | Peripheral ID1 | 0x000000B0 |
0xE000EFE8 | Peripheral ID2 | 0x0000000B |
0xE000EFEC | Peripheral ID3 | 0x00000000 |
0xE000EFF0 | Component ID0 | 0x0000000D |
0xE000EFF4 | Component ID1 | 0x000000E0 |
0xE000EFF8 | Component ID2 | 0x00000005 |
0xE000EFFC | Component ID3 | 0x000000B1 |
See the ARMv7-M Architectural Reference Manual and
the ARM CoreSight Components Technical Reference Manual for
more information about the SCS CoreSight identification registers,
and their addresses and access types.
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