7.1.1. Cortex-M3 ROM table identification and entries

Table 7.1 shows the ROM table identification registers and values for debugger detection. This permits debuggers to identify the processor and its debug capabilities.

Table 7.1. Cortex-M3 ROM table identification values

0xE00FFFD0Peripheral ID40x00000004

Component and Peripheral ID register formats in the ARMv7-M Architectural Reference Manual

0xE00FFFD4Peripheral ID50x00000000
0xE00FFFD8Peripheral ID60x00000000
0xE00FFFDCPeripheral ID70x00000000
0xE00FFFE0Peripheral ID00x000000C3
0xE00FFFE4Peripheral ID10x000000B4
0xE00FFFE8Peripheral ID20x0000000B
0xE00FFFECPeripheral ID30x00000000
0xE00FFFF0Component ID00x0000000D
0xE00FFFF4Component ID10x00000010
0xE00FFFF8Component ID20x00000005
0xE00FFFFCComponent ID30x000000B1

These are the default values for the Peripheral ID registers if the ROM table has not been configured at implementation. Your implementation might use these registers to identify the manufacturer and part number for the device.

The Component ID registers identify this as a CoreSight ROM table.


The Cortex-M3 ROM table only supports word size transactions.

Table 7.2 shows the CoreSight components that the Cortex-M3 ROM table points to. The values depend on the implemented debug configuration.

Table 7.2. Cortex-M3 ROM table components

0xE00FF000SCS0xFFF0F003See System Control Space
0xE00FF004DWT0xFFF02003[a]See Table 8.1
0xE00FF008FPB0xFFF03003[b]See Table 7.7
0xE00FF00CITM0xFFF01003[c]See Table 9.1
0xE00FF010TPIU0xFFF41003[d] See Table 11.1.
0xE00FF014ETM0xFFF42003[e]See Chapter 10 Embedded Trace Macrocell.
0xE00FF018End marker0x00000000See DAP accessible ROM table in the ARMv7-M Architectural Reference Manual.

[a] Reads as 0xFFF02002 if no watchpoints are implemented.

[b] Reads as 0xFFF03002 if no breakpoints are implemented.

[c] Reads as 0xFFF01002 if no ITM is implemented.

[d] Reads as 0xFFF41002 if no TPIU is implemented.

[e] Reads as 0xFFF42002 if no ETM is implemented.

The ROM table entries point to the debug components of the processor. The offset for each entry is the offset of that component from the ROM table base address, 0xE00FF000.

See the ARMv7-M Architectural Reference Manual and the ARM CoreSight Components Technical Reference Manual for more information about the ROM table ID and component registers, and their addresses and access types.

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