Cortex-M3 Technical Reference Manual: 7.1.1. Cortex-M3 ROM table identification and entries

7.1.1. Cortex-M3 ROM table identification and entries

Table 7.1 shows the ROM table identification registers and values for debugger detection. This permits debuggers to identify the processor and its debug capabilities.

Table 7.1. Cortex-M3 ROM table identification values

Address	Register	Value	Description
`0xE00FFFD0`	Peripheral ID4	`0x00000004`	Component and Peripheral ID register formats in the ARMv7-M Architectural Reference Manual
`0xE00FFFD4`	Peripheral ID5	`0x00000000`
`0xE00FFFD8`	Peripheral ID6	`0x00000000`
`0xE00FFFDC`	Peripheral ID7	`0x00000000`
`0xE00FFFE0`	Peripheral ID0	`0x000000C3`
`0xE00FFFE4`	Peripheral ID1	`0x000000B4`
`0xE00FFFE8`	Peripheral ID2	`0x0000000B`
`0xE00FFFEC`	Peripheral ID3	`0x00000000`
`0xE00FFFF0`	Component ID0	`0x0000000D`
`0xE00FFFF4`	Component ID1	`0x00000010`
`0xE00FFFF8`	Component ID2	`0x00000005`
`0xE00FFFFC`	Component ID3	`0x000000B1`

These are the default values for the Peripheral ID registers if the ROM table has not been configured at implementation. Your implementation might use these registers to identify the manufacturer and part number for the device.

The Component ID registers identify this as a CoreSight ROM table.

Note

The Cortex-M3 ROM table only supports word size transactions.

Table 7.2 shows the CoreSight components that the Cortex-M3 ROM table points to. The values depend on the implemented debug configuration.

Table 7.2. Cortex-M3 ROM table components

Address	Component	Value	Description
`0xE00FF000`	SCS	`0xFFF0F003`	See System Control Space
`0xE00FF004`	DWT	`0xFFF02003`^[a]	See Table 8.1
`0xE00FF008`	FPB	`0xFFF03003`^[b]	See Table 7.7
`0xE00FF00C`	ITM	`0xFFF01003`^[c]	See Table 9.1
`0xE00FF010`	TPIU	`0xFFF41003`^[d]	See Table 11.1.
`0xE00FF014`	ETM	`0xFFF42003`^[e]	See Chapter 10 Embedded Trace Macrocell.
`0xE00FF018`	End marker	`0x00000000`	See DAP accessible ROM table in the ARMv7-M Architectural Reference Manual.
`0xE00FFFCC`	SYSTEM ACCESS	`0x00000001`
^[a]Reads as `0xFFF02002` if no watchpoints are implemented. ^[b]Reads as `0xFFF03002` if no breakpoints are implemented. ^[c]Reads as `0xFFF01002` if no ITM is implemented. ^[d]Reads as `0xFFF41002` if no TPIU is implemented. ^[e]Reads as `0xFFF42002` if no ETM is implemented.

The ROM table entries point to the debug components of the processor. The offset for each entry is the offset of that component from the ROM table base address, 0xE00FF000.

See the ARMv7-M Architectural Reference Manual and the ARM CoreSight Components Technical Reference Manual for more information about the ROM table ID and component registers, and their addresses and access types.

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