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The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. When handling exceptions:
All exceptions are handled in Handler mode.
Processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the Interrupt Service Routine (ISR).
The vector is fetched in parallel to the state saving, enabling efficient interrupt entry.
The processor supports tail-chaining that enables back-to-back interrupts without the overhead of state saving and restoration.
You configure the number of interrupts, and bits of interrupt priority, during implementation. Software can choose only to enable a subset of the configured number of interrupts, and can choose how many bits of the configured priorities to use.
Vector table entries are compatible with interworking between ARM and Thumb instructions. This causes bit [0] of the vector value to load into the Execution Program Status Register (EPSR) T-bit on exception entry. All populated vectors in the vector table entries must have bit [0] set. Creating a table entry with bit [0] clear generates an INVSTATE fault on the first instruction of the handler corresponding to this vector.
| Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. | ARM DDI 0337I |
| Non-Confidential | |
| PDF version | |
| Home > Programmers Model > Exceptions |