Cortex-M3 Technical Reference Manual: 5.3. MPU programmers model

Cortex-M3 Technical Reference Manual

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5.3. MPU programmers model

Table 5-5 shows the MPU registers. These registers are described in the ARMv7-M Architecture Reference Manual.

Table 5.1. MPU registers

Address	Name	Type	Reset	Description
`0xE000ED90`	MPU_TYPE	RO	`0x00000800`^[a]	MPU Type Register
`0xE000ED94`	MPU_CTRL	RW	`0x00000000`	MPU Control Register
`0xE000ED98`	MPU_RNR	RW	`0x00000000`	MPU Region Number Register
`0xE000ED9C`	MPU_RBAR	RW	`0x00000000`	MPU Region Base Address Register
`0xE000EDA0`	MPU_RASR	RW	`0x00000000`	MPU Region Attribute and Size Register
`0xE000EDA4`	MPU_RBAR_A1		`0x00000000`	MPU alias registers
`0xE000EDA8`	MPU_RASR_A1		`0x00000000`
`0xE000EDAC`	MPU_RBAR_A2		`0x00000000`
`0xE000EDB0`	MPU_RASR_A2		`0x00000000`
`0xE000EDB4`	MPU_RBAR_A3		`0x00000000`
`0xE000EDB8`	MPU_RASR_A3		`0x00000000`
^[a]If the MPU is not present in the implementation, then this register reads as zero.

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