5.3. MPU programmers model

Table 5-5 shows the MPU registers. These registers are described in the ARMv7-M Architecture Reference Manual.

Table 5.1. MPU registers

AddressNameType

Reset

Description
0xE000ED90MPU_TYPERO0x00000800[a]MPU Type Register
0xE000ED94MPU_CTRLRW0x00000000MPU Control Register
0xE000ED98MPU_RNRRW0x00000000MPU Region Number Register
0xE000ED9CMPU_RBARRW0x00000000MPU Region Base Address Register
0xE000EDA0MPU_RASRRW0x00000000MPU Region Attribute and Size Register
0xE000EDA4MPU_RBAR_A1 0x00000000MPU alias registers
0xE000EDA8MPU_RASR_A1 0x00000000
0xE000EDACMPU_RBAR_A2 0x00000000
0xE000EDB0MPU_RASR_A2 0x00000000
0xE000EDB4MPU_RBAR_A3 0x00000000
0xE000EDB8MPU_RASR_A3 0x00000000

[a] If the MPU is not present in the implementation, then this register reads as zero.


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