1.5.3. Architecture and protocol information

The processor complies with, or implements, the specifications described in:

This book complements architecture reference manuals, architecture specifications, protocol specifications, and relevant external standards. It does not duplicate information from these sources.

ARM architecture

The processor implements the ARMv7-M architecture profile. See the ARMv7-M Architecture Reference Manual.

For more information about architectural compliance, see Architecture and protocol information on page 1-9.

Bus architecture

The processor provides three primary bus interfaces implementing a variant of the AMBA 3 AHB-Lite protocol. The processor implements an interface for CoreSight and other debug components using the AMBA 3 APB protocol. See:

  • the ARM AMBA 3 AHB-Lite Protocol (v1.0)

  • the ARM AMBA 3 APB Protocol Specification.

Debug

The debug features of the processor implement the ARM debug interface architecture. See the ARM Debug Interface v5 Architecture Specification. The processor also implements debug features defined by the ARMv7-M. See the ARMv7-M Architecture Reference Manual.

Embedded Trace Macrocell

The trace features of the processor implement version 3.4 of the ARM Embedded Trace Macrocell architecture. See the ARM Embedded Trace Macrocell Architecture Specification.

Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.ARM DDI 0337I
Non-Confidential