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The processor contains an Advanced High-performance Bus Access Port (AHB-AP) interface for debug accesses. An external Debug Port (DP) component accesses this interface. The Cortex-M3 system supports three possible DP implementations:
The Serial Wire JTAG Debug Port (SWJ-DP). The SWJ-DP is a standard CoreSight debug port that combines JTAG-DP and Serial Wire Debug Port (SW-DP).
The SW-DP. This provides a two-pin interface to the AHB-AP port.
No DP present. If no debug functionality is present within the processor, a DP is not required.
The two DP implementations provide different mechanisms for debug access to the processor. Your implementation must contain only one of these components.
Your implementation might contain an alternative implementer-specific DP instead of SW-DP or SWJ-DP. See your implementer for details.
For more detailed information on the DP components, see the CoreSight Components Technical Reference manual.
For more information on the AHB-AP, see Chapter 7 Debug.
The DP and AP together are referred to as the Debug Access Port (DAP).
For more detailed information on the debug interface, see the ARM Debug Interface v5 Architecture Specification.
| Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. | ARM DDI 0337I |
| Non-Confidential | |
| PDF version | |
| Home > Functional Description > Interfaces > Debug Port AHB-AP interface |