Addition of configurable data value comparison to the DWT module.

Addition of a MATCHED bit to DWT_FUNCTION.

Addition of configurable ETMFIFOFULL stalling functionality to the processor and the ETM.

Addition of SWV Mode to the ITM.

CPUID Base Register VARIANT field changed to indicate Rev1.

Cortex-M3 Rev0 Bit-band accesses in BE8 mode required access sizes to be byte. Cortex-M3 Rev1 has been changed so that BE8 bit-band accesses function with any access size.

Addition of a configuration bit called STKALIGN to ensure that all exceptions have eight-byte stack alignment.

Addition of the Auxiliary Fault Status Register at address 0xE000ED3C. To set this register, a 32-bit input bus called AUXFAULT has been added.

Addition of HTM support.

ICode and DCode cacheable and bufferable HPROT values permanently tied to write-through.

Addition of the SWJ-DP. This is the standard CoreSight™ debug port that combines JTAG-DP and SW-DP.

Addition of DWT_PCSR Register at address 0xE000101C.

Errata fixes to the r0p0 release.