Cortex-M3 Technical Reference Manual Revision r2p1
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10.3.7. ID Register, ETMIDR

The ETMIDR characteristics are:

Purpose

Holds the ETM architecture variant, and defines the programmers model for the ETM.

Usage constraints

There are no usage constraints.

Configurations

This register is only available if the processor is configured to use the ETM.

Attributes

See the register summary in Table 10.6.

Figure 10.6 shows the ETMIDR bit assignments.

Figure 10.6. ETMIDR bit assignments

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Table 10.11 shows the ETMIDR bit assignments.

Table 10.11. ETMIDR bit assignments

Bits

Name

Function

[31:24]

Implementer code

These bits identify ARM as the implementer of the processor. The value of these bits is 0b01000001.

[23:21]

-

Reserved.

[20]Branch packet encoding

The value of this bit is 1, indicating that alternative branch packet encoding is implemented.

[19]

Security Extensions support

The value of this bit is 0, indicating that the ETM behaves as if the processor is in Secure state at all times.

[18]32-bit Thumb instruction tracing

The value of this bit is 1, indicating that a 32-bit Thumb instruction is traced as a single instruction.

[17]-

Reserved.

[16]Load PC first

The value of this bit is 0, indicating that data tracing is not supported.

[15:12]

Processor family

The value of these bits is 0b1111, indicating that the processor family is not identified in this register.

[11:8]

Major ETM architecture version

The value of these bits is 0b0010, indicating major architecture version number 3, ETMv3.

[7:4]

Minor ETM architecture version

The value of these bits is 0b0101, indicating minor architecture version number 5.

[3:0]

Implementation revision

The value of these bits is 0b0011, indicating implementation revision, 3.


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