Appendix A. Revisions

This appendix describes the technical changes between released issues of this book.

Table A.1. Differences between issue E and issue F

ChangeLocation
Introductory processor information updatedIssue H distributes this information between About the processor and Features and removes duplicate information from these sections.
Processor block diagram updatedFigure 2.1

Introductory information added, including:

  • TPIU subsection

  • Addition of note to SW/SWJ-DP subsection

  • ROM table subsection.

Issue H removes this information.
Introductory processor core information updated
APB bus now version 3.0Architecture and protocol information

Configurable options information expanded to include:

  • Added DWT configurability information

  • New subsections for ITM, AHB-AP, FPB and Observation.

Configurable options
New subsection added to list changes in functionality between r1p1 and r2p0Differences in functionality between r1p1 and r2p0
Information about the programmers model updatedIssue H distributes this information between Operating modes and Operating states.
Definition of ICI field of Execution Program Status Register updatedIssue H removes this information.
Table of nonsupported Thumb instructions removed. 
Second footnote on Table 5-1 removed.Issue H removes this information.
Addition of note to vector table and reset description
Description of SLEEPING and SLEEPDEEP signals updated.
Description of extending sleep functionality added
Addition of Auxiliary Control RegisterAuxiliary Control Register, ACTLR
Irq 0 to 31 Priority Register amended to Irq 0 to 3 Priority RegisterIssue H removes this information.
Irq 236 to 239 Priority Register amended to Irq 224 to 239 Priority Register
HCLK changed to FCLK
Addition of ascending MPU region priority informationAbout the MPU
Extra paragraph added.Issue H removes this information.
Debug Core Register Selector Register REGSEL bit field function updated
Paragraph added about removing FPB
Addition of note about configuring flash patch registers to be present or notFPB programmers model
First bullet point updatedAbout the DWT
Addition of note about configuring DWT registers to be present or notDWT Programmers Model
DWT Control Register reset state updatedTable 8.1
DWT Control Register bit assignments updatedIssue H removes this information.
Addition of note about configuring ITM registers to be present or notITM programmers model
ITM Trace Control Register TSENA field bit function updated
Addition of note about configuring AHB-AP registers to be present or notAHB-AP programmers model
AHB-AP Banked Data Register DATA field reset value removedIssue H removes this information.
Addition of information about absence of debug functionalityAbout debug
Information about exclusive memory accesses updatedIssue H removes this information.
Note about bit-band accesses updatedBit-banding
ETM block diagram updatedFigure 10.1
HCLK and CLK replaced by FCLKIssue H removes this information.
ETM Trigger Even Register description upgraded
ETM Status Register description updated
TraceEnable register replaced by Trace Start/Stop Resource Control
TraceEnable Control 2 register added
Lock Status Register added
Description of FIFOFULL Region Register added
Description of FIFOFULL Level Register updated
Description of CoreSight Trace ID Register updated
Description ETM Control Register implementation bits expandedMain Control Register, ETMCR
Description of TraceEnable Control 1 Register updatedTraceEnable Control 1 Register, ETMTECR1
Description ETM ID Register updated to reflect revision 2ID Register, ETMIDR
Subsection describing ETM Event Resources addedResources
Subsection describing Cross Trigger Interface addedRecommended CTI connections
Branch status interface section updatedIssue H removes this information.
Note about HADDRICore and HTRANSICore removed
Example of an opcode sequence timing diagram updated
Description of APB interface inputs added
Addition of note about configuring TPIU registers to be present or notTPIU programmers model

The following TPIU registers removed from summary table and descriptions:

  • Trigger control registers

  • EXTCTL port registers

  • Test pattern registers.

Issue H removes this information.

The following TPIU registers added to the summary table and descriptions:

  • Integration Register: TRIGGER

  • Integration Mode Control Register

  • Integration Register: FIFO data 0

  • Integration Register: FIFO data 1

  • Claim tag set register

  • Claim tag clear register

  • Device ID register

  • PID registers

  • CID registers.


Table A.2. Differences between issue F and issue G

ChangeLocation
Wake-up Interrupt Controller (WIC) added to Cortex-M3 block diagramFigure 2.1
Section 1-2 and section 1-3 combinedIssue H distributes this information between Features, Interfaces, and Configurable options.
New subsection added to list changes in functionality between r1p1 and r2p0Differences in functionality between r1p1 and r2p0
New subsection added to describe the WICLow power modes
New bullet point to describe FIXHMASTERTYPE pinDifferences in functionality between r1p1 and r2p0
Table of supported instruction removedIssue H reinstates this information in Table 3.1.
More information added about the stacked xPSRIssue H removes this information.
Reset value of Configuration Control Register changed to 0x00000200
System and Vendor_SYS memory regions added to table of memory region permissions
Memory region for Private Peripheral Bus changed to +0000000
SLEEPHOLDREQ changed to SLEEPHOLDREQn
SLEEPHOLDACK changed to SLEEPHOLDACKn
DEEPSLEEP signal changed to SLEEPDEEP
DBGRESTARTACK changed to DBGRESTARTED
DBGRESTARTREQ changed to DBGRESTART
New subsection added to describe the WIC
Address of Irq 224 to 239 Priority Register changed to 0xE000E4EC
Enhanced description of function of C_MASKINTS field
Settings for DWT Function Registers updated
Minor change to timing information of ETMIA
Change to timing information for ETMIVALIDIssue H removes this information.
SLEEPHOLDREQn removed from table of miscellaneous input ports timing parameters
Table of low power input ports timing parameters added
FIXHMASTERTYPE added to table of debug input ports timing parameters
Input changed to Output in table header
SLEEPING, SLEEPDEEP, and SLEEPHOLDACKn removed from table of miscellaneous output ports timing parameters
SLEEPDEEP, SLEEPING, SLEEPHOLDREQ, and SLEEPHOLDACK removed
New section added to describe the low power interface signals
New section added to describe the WIC interface signals
SLEEPHOLDACKn removed from table of miscellaneous signals
Asserted changed to de-asserted in the description of SLEEPHOLDREQn in table of low power interface signals
FIXMASTERTPYE added to list of AHB-AP interface signals

Note

Issue H of this book is significantly reorganized and simplified to eliminate duplication of information contained in the ARM Architecture Reference Manual and other ARM documentation.

Table A.3. Differences between issue G and issue H

ChangeLocation
Chapter 1 simplified to provide only a high-level description of the processor. Some information to Chapter 2.

Chapter 1 Introduction

Chapter 2 Functional Description

Removed the following sections from Chapter 1:

  • Execution pipeline stages

  • Prefetch unit

  • Branch target forwarding

  • Store buffers.

See the ARMv7-M Architecture Reference Manual and the implementation documentation for the processor.
Added functional description chapterChapter 2 Functional Description
Simplified description of the programmers model and modes of operation and execution

About the programmers model

Modes of operation and execution

Added cycle counts to instruction set summaryInstruction set summary
Descriptions of the memory system and of exceptions moved to Chapter 3.Chapter 3 Programmers Model
Component-specific registers moved from System Control chapter to appropriate chapters within the manual.Chapter 4 System Control
Deleted Clocking and Resets chapter.See the implementation documentation for the processor.
Deleted Power Management chapter.
In the Memory Protection Unit and Nested Vector Interrupt Controller chapters, removed description of architecturally-defined registers.
Reorganized debug description into a single chapter. Chapter 7 Debug
Deleted Bus Interface chapter and moved high-level information to appropriate chapters.

Chapter 1 Introduction

Chapter 2 Functional Description

Chapter 3 Programmers Model

Deleted Debug Port chapter and incorporated general information from this chapter into chapters 2 and 7.

Chapter 2 Functional Description

Chapter 7 Debug

Moved information from the System Debug chapter to create new chapters for the Data Watchpoint and Trace Unit and the Instrumentation Trace Macrocell Unit.

Chapter 8 Data Watchpoint and Trace Unit

Chapter 9 Instrumentation Trace Macrocell Unit

Reorganized Embedded Trace Macrocell description into a single chapter.Chapter 10 Embedded Trace Macrocell
Removed signal information and architecturally-defined register descriptions from the Trace Port Interface Unit chapter.Removed duplicate information. See the ARMv7-M Architecture Reference Manual and the implementation documentation for the processor.
Moved instruction timing information to chapter 3.Instruction set summary
Removed AC Characteristics and Signal Descriptions chapters.See the implementation documentation for the processor.

Table A.4. Differences between issue H and issue I

ChangeLocation
Updated Bus interfaces information.Bus interfaces
Added informaion on Private Peripheral BusPrivate Peripheral Bus (PPB)
Updated Load/store timings information.Load/store timings
Updated Exclusive monitor information.Exclusive monitor
Updated Reset values for Register summary information.Table 4.1
Reset values updated.Table 4.1
Updated Reset values for MPU register information.Table 5.1
Changed address range of NVIC_IPR registers.Table 6.1
Updated values for the Cortex-M3 ROM table information and added Peripheral IDs 5-7.Table 7.1
Added Timestamp format information.Timestamp format
Added ETM register descriptions.Table 10.6
Added ETMCNTRLDVR1 ETM register. Table 10.6
Changed reset values for ETMVCCR and ETMCCER.Table 10.6
Updated ETMCR register bit assignments.Table 10.7
Updated ETMCCR bit assignments.Table 10.8
Updated ETMCCER bit assignments.Table 10.12
Aded TPIU_DEVTYPE TPIU Register. Changed reset values.Table 11.1
Updated TPIU Formatter informationTPIU Formatter
Replaced FIFO 0 with ETM.

Integration ETM Data

Integration ITM Data

Replaced FIFO 1 with ITM

Integration ETM Data

Integration ITM Data

Added TPIU_DEVTYPE Register description.TPIU_DEVTYPE

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