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The ETM-M3 has the following external interfaces:
A 32-bit Advanced Trace Bus provides trace output from the macrocell. See the AMBA 3 ATB Protocol Specification for more information about this interface.
An Advanced Peripheral Bus provides the control interface for the macrocell. See the AMBA 3 APB Protocol Specification for more information about this interface.
Your implementation can provide a Cross Trigger Interface to manage the interconnection of trigger and control signals between the processor core, ETM, and TPIU. The implementation of your Cortex-M3 processor determines which ETM functions are visible to the CTI.
Table 10.4 and Table 10.5 show the recommended CTI connections for Cortex-M3 systems.
These tables show the ARM standard connections, but the actual connections are implementation-defined. Check the documentation from the supplier of your device for any changes to these connections.
Table 10.4. Input connections
| Trigger bit | Source signal | Source device | Comments |
|---|---|---|---|
| [7] | ETMTRIGOUT | ETM | Recommended if ETM is present. |
| [6] | ETMTRIGGER[2] | DWT | Recommended. |
| [5] | ETMTRIGGER[1] | DWT | Recommended. |
| [4] | ETMTRIGGER[0] | DWT | Recommended. |
| [3] | ACQCOMP | ETB | Recommended if an Embedded Trace Buffer (ETB) is present. If multiple cores share a single ETB, you must only connect to the CTI of one of the cores. |
| [2] | FULL | ETB | |
| [1] | User Defined | - | - |
| [0] | HALTED | Core | Compulsory. |
Table 10.5. Trigger output connections
| Trigger bit | Destination signal | Destination device | Comments |
|---|---|---|---|
| [7] | User defined | - | - |
| [6] | User defined | - | - |
| [5] | ETMEXTIN[1] | ETM | Compulsory if ETM is present. |
| [4] | ETMEXTIN[0] | ETM | Compulsory if ETM is present. |
| [3] | INTISR[y] | NVIC | Recommended if an ETB is present. If multiple cores share a single ETB, you must only connect to the CTI of one of the cores. |
| [2] | INTISR[x] | NVIC | Compulsory. Any interrupt can be used. |
| [1] | User defined | - | - |
| [0] | EDBGRQ | Core | Compulsory. |
| Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. | ARM DDI 0337I |
| Non-Confidential | |
| PDF version | |
| Home > Embedded Trace Macrocell > ETM functional description > Interfaces |