10.2.8. Interfaces

The ETM-M3 has the following external interfaces:

ATB

A 32-bit Advanced Trace Bus provides trace output from the macrocell. See the AMBA 3 ATB Protocol Specification for more information about this interface.

APB

An Advanced Peripheral Bus provides the control interface for the macrocell. See the AMBA 3 APB Protocol Specification for more information about this interface.

CTI

Your implementation can provide a Cross Trigger Interface to manage the interconnection of trigger and control signals between the processor core, ETM, and TPIU. The implementation of your Cortex-M3 processor determines which ETM functions are visible to the CTI.

Recommended CTI connections

Table 10.4 and Table 10.5 show the recommended CTI connections for Cortex-M3 systems.

Note

These tables show the ARM standard connections, but the actual connections are implementation-defined. Check the documentation from the supplier of your device for any changes to these connections.

Table 10.4. Input connections

Trigger bitSource signalSource deviceComments
[7]ETMTRIGOUTETMRecommended if ETM is present.
[6]ETMTRIGGER[2]DWTRecommended.
[5]ETMTRIGGER[1]DWTRecommended.
[4]ETMTRIGGER[0]DWTRecommended.
[3]ACQCOMPETBRecommended if an Embedded Trace Buffer (ETB) is present. If multiple cores share a single ETB, you must only connect to the CTI of one of the cores.
[2]FULLETB
[1]User Defined--
[0]HALTEDCoreCompulsory.

Table 10.5. Trigger output connections

Trigger bitDestination signalDestination deviceComments
[7]User defined--
[6]User defined--
[5]ETMEXTIN[1]ETMCompulsory if ETM is present.
[4]ETMEXTIN[0]ETMCompulsory if ETM is present.
[3]INTISR[y]NVICRecommended if an ETB is present. If multiple cores share a single ETB, you must only connect to the CTI of one of the cores.
[2]INTISR[x]NVICCompulsory. Any interrupt can be used.
[1]User defined--
[0]EDBGRQCoreCompulsory.

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