Cortex-M3 Technical Reference Manual Revision r2p1
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10.3.5. System Configuration Register, ETMSCR

The ETMSCR characteristics are:

Purpose

Shows the ETM features supported by the implementation of the ETM macrocell.

Usage constraints

There are no usage constraints.

Configurations

This register is only available if the processor is configured to use the ETM.

Attributes

See the register summary in Table 10.6.

Figure 10.4 shows the ETMSCR bit assignments.

Figure 10.4. ETMSCR bit assignments

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Table 10.9 shows the ETMSCR bit assignments.

Table 10.9. ETMSCR bit assignments

Bits

Name

Function

[31:18]-Reserved.
[17]No Fetch comparisonsThe value of this bit is 1, indicating that fetch comparisons are not implemented.
[16:15]-Reserved.
[14:12](N-1)

These bits give the number of supported processors minus 1. The value of these bits is 0b000, indicating that there is only one processor connected.

[11]Port mode supported

This bit reads as 1 if the currently selected port mode is supported. This has no effect on the TPIU trace port.

[10]Port size supported

This bit reads as 1 if the currently selected port size is supported. This has no effect on the TPIU trace port.

[9]Maximum port size [3]Maximum ETM port size bit [3]. This bit is used in conjunction with bits [2:0]. Its value is 0. This has no effect on the TPIU trace port.

[8]

FIFOFULL supported

The value of this bit is 1, indicating that FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETMCCR.

[7:4]

-Reserved, Read-As-Zero.

[3]

-Reserved, Read-As-One.

[2:0]

Maximum port size [2:0]

Maximum ETM port size bits [2:0]. These bits are used in conjunction with bit [9]. The value of these bits is 0b001.


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