Cortex-M3 Technical Reference Manual Revision r2p1
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10.3.9. TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR

The ETMTESSEICR characteristics are:

Purpose

Specifies the EmbeddedICE watchpoint comparator inputs that are used to control the start/stop resource.

Usage constraints

There are no usage constraints.

Configurations

This register is only available if the processor is configured to use the ETM.

Attributes

See the register summary in Table 10.6.

Figure 10.8 shows the ETMTESSEICR bit assignments.

Figure 10.8. ETMTESSEICR bit assignments

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Table 10.13 shows the ETMTESSEICR bit assignments.

Table 10.13. ETMTESSEICR bit assignments

Bits

Name

Function

[31:20]-Reserved, Read-as-zero.

[19:16]

Stop resource selection

Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] corresponds to input 2, bit [18] corresponds to input 3, and bit [19] corresponds to input 4.

[15:4]-Reserved, Read-As-Zero.

[3:0]

Start resource selection

Setting any of these bits to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] corresponds to input 2, bit [2] corresponds to input 3, and bit [3] corresponds to input 4.


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