A subset of the Thumb instruction set, defined in the ARMv7-M Architecture Reference Manual.

Banked Stack Pointer (SP).

Hardware integer divide instructions, SDIV and UDIV.

Handler and Thread modes.

Thumb and Debug states.

Support for interruptible-continued instructions LDM, STM, PUSH, and POP for low interrupt latency.

Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit.

Support for ARMv6 big-endian byte-invariant or little-endian accesses.

Support for ARMv6 unaligned accesses.

External interrupts, configurable from 1 to 240.

Bits of priority, configurable from 3 to 8.

Dynamic reprioritization of interrupts.

Priority grouping. This enables selection of preempting interrupt levels and non preempting interrupt levels.

Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts.

Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead.

Optional Wake-up Interrupt Controller (WIC), providing ultra-low power sleep mode support.

Eight memory regions.

Sub Region Disable (SRD), enabling efficient use of memory regions.

The ability to enable a background region that implements the default memory map attributes.

Three Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and System bus interfaces.

Private Peripheral Bus (PPB) based on Advanced Peripheral Bus (APB) interface.

Bit-band support that includes atomic bit-band write and read operations.

Memory access alignment.

Write buffer for buffering of write data.

Exclusive access transfers for multiprocessor systems.

Debug access to all memory and registers in the system, including access to memory mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is asserted.

Serial Wire Debug Port (SW-DP) or Serial Wire JTAG Debug Port (SWJ-DP) debug access.

Optional Flash Patch and Breakpoint (FPB) unit for implementing breakpoints and code patches.

Optional Data Watchpoint and Trace (DWT) unit for implementing watchpoints, data tracing, and system profiling.

Optional Instrumentation Trace Macrocell (ITM) for support of printf() style debugging.

Optional Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer (TPA), including Single Wire Output (SWO) mode.

Optional Embedded Trace Macrocell (ETM) for instruction trace.