Cortex-M3 Technical Reference Manual: 3.8. Processor core register summary

3.8. Processor core register summary

The processor has the following 32-bit registers:

13 general-purpose registers, R0-R12
Stack Pointer (SP), R13 alias of banked registers, SP_process and SP_main
Link Register (LR), R14
Program Counter (PC), R15
Special-purpose Program Status Registers, (xPSR).

Figure 3.3 shows the processor register set.

Figure 3.3. Processor register set

The general-purpose registers R0-R12 have no special architecturally-defined uses. Most instructions that can specify a general-purpose register can specify R0-R12.

Low registers: Registers R0-R7 are accessible by all instructions that specify a general-purpose register.
High registers: Registers R8-R12 are accessible by all 32-bit instructions that specify a general-purpose register.
Registers R8-R12 are not accessible by any 16-bit instructions.

Registers R13, R14, and R15 have the following special functions:

Stack pointer: Register R13 is used as the Stack Pointer (SP). Because the SP ignores writes to bits [1:0], it is autoaligned to a word, four-byte boundary.
Handler mode always uses SP_main, but you can configure Thread mode to use either SP_main or SP_process.
Link register: Register R14 is the subroutine Link Register (LR).
The LR receives the return address from PC when a Branch and Link (BL) or Branch and Link with Exchange (BLX) instruction is executed.
The LR is also used for exception return.
At all other times, you can treat R14 as a general-purpose register.
Program counter: Register R15 is the Program Counter (PC).
Bit [0] is always 0, so instructions are always aligned to word or halfword boundaries.

See the ARMv7-M Architecture Reference Manual for more information.

Copyright © 2005-2008, 2010 ARM Limited. All rights reserved.	ARM DDI 0337I
Non-Confidential
PDF version