3.9.1. Exception handling

The processor implements advanced exception and interrupt handling, as described in the ARMv7-M Architecture Reference Manual.

To reduce interrupt latency, the processor implements both interrupt late-arrival and interrupt tail-chaining mechanisms, as defined by the ARMv7-M architecture:

The processor exception model has the following implementation-defined behavior in addition to the architecturally defined behavior:

To minimize interrupt latency, the processor abandons any divide instruction to take any pending interrupt. On return from the interrupt handler, the processor restarts the divide instruction from the beginning The processor implements the Interruptible-continuable Instruction field. Load multiple (LDM) operations and store multiple (STM) operations are interruptible. The EPSR holds the information required to continue the load or store multiple from the point where the interrupt occurred.

This means that software must not use load-multiple or store-multiple instructions to access a device or access a memory region that is read-sensitive or sensitive to repeated writes. The software must not use these instructions in any case where repeated reads or writes might cause inconsistent results or unwanted side-effects.

Base register update in LDM and STM operations

There are cases when an LDM or STM updates the base register:

  • When the instruction specifies base register write-back, the base register changes to the updated address. An abort restores the original base value.

  • When the base register is in the register list of an LDM, and is not the last register in the list, the base register changes to the loaded value.

An LDM or STM is restarted rather than continued if:

  • the instruction faults

  • the instruction is inside an IT.

If an LDM has completed a base load, it is continued from before the base load.

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