Cortex-M3 Technical Reference Manual: 10.3.2. Register summary

10.3.2. Register summary

Table 10.6 shows the ETM registers.

Table 10.6. ETM registers

Address	Name	Reset	Type	Description
`0xE0041000`	ETMCR	`0x00000411`	RW	Main Control Register, ETMCR
`0xE0041004`	ETMCCR	`0x8C802000`	RO	Configuration Code Register, ETMCCR
`0xE0041008`	ETMTRIGGER	-	RW	Trigger Event Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041010`	ETMSR	-	RW	ETM Status Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041014`	ETMSCR	`0x00020D09`	RO	System Configuration Register, ETMSCR
`0xE0041020`	ETMTEEVR	-	RW	TraceEnable Event Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041024`	ETMTECR1	-	RW	TraceEnable Control 1 Register, ETMTECR1
`0xE0041028`	ETMFFLR	-	RW	FIFOFULL Level Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041140`	ETMCNTRLDVR1	-	RW	Free-running counter reload value
`0xE00411E0`	ETMSYNCFR	`0x00000400`	RO	Synchronisation Frequency Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE00411E4`	ETMIDR	`0x4114F253`	RO	ID Register, ETMIDR
`0xE00411E8`	ETMCCER	`0x18541800`	RO	Configuration Code Extension Register, ETMCCER
`0xE00411F0`	ETMTESSEICR	-	RW	TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
`0xE00411F8`	ETMTSEVR	-	RW	Timestamp Event Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041200`	ETMTRACEIDR	`0x00000000`	RW	CoreSight Trace ID Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041208`	ETMIDR2	0x00000000	RO	ETM ID Register 2. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041314`	ETMPDSR	`0x00000001`	RO	Device Power-Down Status Register, ETMPDSR
`0xE0041EE0`	ITMISCIN	-	RO	Integration Test Miscellaneous Inputs, ITMISCIN
`0xE0041EE8`	ITTRIGOUT	-	WO	Integration Test Trigger Out, ITTRIGOUT
`0xE0041EF0`	ETM_ITATBCTR2	-	RO	ETM Integration Test ATB Control 2, ETM_ITATBCTR2
`0xE0041EF8`	ETM_ITATBCTR0	-	WO	ETM Integration Test ATB Control 0, ETM_ITATBCTR0
`0xE0041F00`	ETMITCTRL	`0x00000000`	RW	Integration Mode Control Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FA0`	ETMCLAIMSET	-	RW	Claim Tag Set Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FA4`	ETMCLAIMCLR	-	RW	Claim Tag Clear Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FB0`	ETMLAR	-	RW	Lock Access Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FB4`	ETMLSR	-	RO	Lock Status Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FB8`	ETMAUTHSTATUS	-	RO	Authentication Status Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FCC`	ETMDEVTYPE	`0x00000013`	RO	CoreSight Device Type Register. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FD0`	ETMPIDR4	`0x00000004`	RO	Peripheral Identification registers. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FD4`	ETMPIDR5	`0x00000000`	RO
`0xE0041FD8`	ETMPIDR6	`0x00000000`	RO
`0xE0041FDC`	ETMPIDR7	`0x00000000`	RO
`0xE0041FE0`	ETMPIDR0	`0x00000024`	RO
`0xE0041FE4`	ETMPIDR1	`0x000000B9`	RO
`0xE0041FE8`	ETMPIDR2	`0x0000003B`	RO
`0xE0041FEC`	ETMPIDR3	`0x00000000`	RO
`0xE0041FF0`	ETMCIDR0	`0x0000000D`	RO	Component Identification registers. See ARM Embedded Trace Macrocell Architecture Specification
`0xE0041FF4`	ETMCIDR1	`0x00000090`	RO
`0xE0041FF8`	ETMCIDR2	`0x00000005`	RO
`0xE0041FFC`	ETMCIDR3	`0x000000B1`	RO

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