10.3.2. Register summary

Table 10.6 shows the ETM registers.

Table 10.6. ETM registers

AddressNameResetTypeDescription
0xE0041000ETMCR0x00000411RWMain Control Register, ETMCR
0xE0041004ETMCCR0x8C802000ROConfiguration Code Register, ETMCCR
0xE0041008ETMTRIGGER-RWTrigger Event Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041010ETMSR-RWETM Status Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041014ETMSCR0x00020D09ROSystem Configuration Register, ETMSCR
0xE0041020ETMTEEVR-RWTraceEnable Event Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041024ETMTECR1-RWTraceEnable Control 1 Register, ETMTECR1
0xE0041028ETMFFLR-RWFIFOFULL Level Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041140ETMCNTRLDVR1-RWFree-running counter reload value
0xE00411E0ETMSYNCFR0x00000400ROSynchronisation Frequency Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE00411E4ETMIDR0x4114F253ROID Register, ETMIDR
0xE00411E8ETMCCER0x18541800ROConfiguration Code Extension Register, ETMCCER
0xE00411F0ETMTESSEICR-RWTraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
0xE00411F8ETMTSEVR-RWTimestamp Event Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041200ETMTRACEIDR0x00000000RWCoreSight Trace ID Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041208ETMIDR20x00000000ROETM ID Register 2. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041314ETMPDSR0x00000001RODevice Power-Down Status Register, ETMPDSR
0xE0041EE0ITMISCIN-ROIntegration Test Miscellaneous Inputs, ITMISCIN
0xE0041EE8ITTRIGOUT-WOIntegration Test Trigger Out, ITTRIGOUT
0xE0041EF0ETM_ITATBCTR2-ROETM Integration Test ATB Control 2, ETM_ITATBCTR2
0xE0041EF8ETM_ITATBCTR0-WOETM Integration Test ATB Control 0, ETM_ITATBCTR0
0xE0041F00ETMITCTRL0x00000000RWIntegration Mode Control Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FA0ETMCLAIMSET-RWClaim Tag Set Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FA4ETMCLAIMCLR-RWClaim Tag Clear Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FB0ETMLAR-RWLock Access Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FB4ETMLSR-ROLock Status Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FB8ETMAUTHSTATUS-ROAuthentication Status Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FCCETMDEVTYPE0x00000013ROCoreSight Device Type Register. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FD0ETMPIDR40x00000004ROPeripheral Identification registers. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FD4ETMPIDR50x00000000RO
0xE0041FD8ETMPIDR60x00000000RO
0xE0041FDCETMPIDR70x00000000RO
0xE0041FE0ETMPIDR00x00000024RO
0xE0041FE4ETMPIDR10x000000B9RO
0xE0041FE8ETMPIDR20x0000003BRO
0xE0041FECETMPIDR30x00000000RO
0xE0041FF0ETMCIDR00x0000000DROComponent Identification registers. See ARM Embedded Trace Macrocell Architecture Specification
0xE0041FF4ETMCIDR10x00000090RO
0xE0041FF8ETMCIDR20x00000005RO
0xE0041FFCETMCIDR30x000000B1RO

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