During the processing of a memory region, the MPU behaves differently because it is checking for faults. The MPU generates three types of fault:

Aborts that are detected by the MPU are taken before any external memory access takes place.

Alignment fault checking is enabled by the A bit in the Control Register CP15 c1. Alignment fault checking is independent of the MPU being enabled. Access permission faults are only generated when the MPU is enabled.

The access control mechanisms of the MPU detect the conditions that produce these faults. If a fault is detected as the result of a memory access, the MPU aborts the access and signals the fault condition to the processor. Status and address information about faults generated by data accesses are held in DFSR and FAR, see Fault status and address. Status information about faults generated by instruction fetches are held in IFSR.

An access violation for a given memory access inhibits any corresponding external access, and an abort is returned to the ARM1156T2-S processor.