Mechanisms that can cause the ARM1156T2-S processor to take an exception because of a memory access are:

Collectively these are called aborts. Accesses that cause aborts are said to be aborted. If the memory request that aborts is an instruction fetch, a Prefetch Abort exception is raised if and when the processor attempts to execute the instruction corresponding to the aborted access. If the aborted access is a data access or a cache maintenance operation, a Data Abort exception is raised.

All Data Aborts, and aborts caused by cache maintenance operations, cause the Data Fault Status Register (DFSR) to be updated so that you can determine the cause of the abort.

For all aborts, excluding imprecise aborts, the Fault Address Register (FAR) is updated with the address that caused the abort. External Data Aborts and Parity Aborts can be imprecise and therefore the FAR does not contain the address of the abort. For more details on imprecise Data Aborts, see Imprecise Data Abort mask in the CPSR/SPSR.

For the precise value stored in the IFAR see c6, Instruction Fault Address Register.

For instruction aborts the value of r14 is used by the abort handler to determine the address that caused the abort.