ARM1156T2-S™ Technical Reference Manual 3.2.5. c0, Cache Type Register

3.2.5. c0, Cache Type Register

The purpose of the Cache Type Register is to provide information about the size and architecture of the cache for the operating system. This enables the operating system to establish how to clean the cache and how to lock it down. Inclusion of this register enables RTOS vendors to produce future-proof versions of their operating systems.

The Cache Type Register is:

in CP15 c0
32-bit read-only
accessible in privileged modes only.

All ARMv4T and later cached processors contain this register. Figure 3.12 shows the arrangement of bits in the register.

Figure 3.12. Cache Type Register format

Table 3.5 shows how the bit values correspond with the Cache Type Register functions.

Table 3.5. Cache Type Register bit functions

Bits	Field	Function
[31:29]	SBZ	Should Be Zero
[28:25]	Ctype	Cache type. The processor supports write back cache, Format C cache lockdown, and Register 7 cache cleaning operations. The C type and S bit provide information about the cache architecture.
[24]	S	Specifies whether the cache is a unified cache or separate instruction and data caches. Always 1 because the ARM1156T2-S processor has separate instruction and data caches.
[23:21]	SBZ	Should Be Zero
[20:18]	Dsize	Data cache size. The Dsize field indicates the data cache size in conjunction with the DM bit. See Table 3.6.
[17:15]	Dassoc	Data cache associativity. See Table 3.7
[14]	DM	The data multiplier bit. Set to b1 when cache absent. The Dsize field indicates the data cache size in conjunction with the DM bit. See Table 3.6.
[13:12]	Dlen	Data cache line length. Set to data cache line length of 8 words (b10), that is 32 bytes. All other values for Len are reserved. Indicates data cache line length.
[11:9]	SBZ	Should Be Zero
[8:6]	Isize	Instruction cache size. The Isize field indicates the instruction cache size in conjunction with the IM bit. See Table 3.6.
[5:3]	Iassoc	The Iassoc field indicates the instruction cache associativity. See Table 3.7.
[2]	IM	The instruction multiplier bit. Set to b1 when cache absent. The instruction size field indicates the instruction cache size in conjunction with the IM bit. See Table 3.6.
[1:0]	Ilen	Instruction cache line length. Set to instruction cache line length of 8 words (b10), that is 32 bytes. All other values for Ilen are reserved.

Table 3.6 shows how the Dsize and Isize fields indicate the size of the instruction cache and data caches respectively.

Table 3.6. Instruction and data cache sizes

Dsize and Isize field	Size
b001	1KB
b010	2KB
b011	4KB
b100	8KB
b101	16KB
b110	32KB
b111	64KB

Table 3.7 shows how the Dassoc and Iassoc fields indicate the associativity of the instruction cache and data caches respectively.

Table 3.7. Instruction and data cache associativity

Dassoc and Iassoc field	Associativity
b000	1-way
b001	2-way
b010	4-way

To use the Cache Type Register read CP15 with:

Opcode_1 set to 0
CRn set to c0
CRm set to c0
Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c0, c0, 1 ;returns cache details

Table 3.8 shows the Cache Type Register default values for an ARM1156T2F-S processor with 16KB cache size and:

separate instruction and data caches
4-way cache associativity
cache line length of eight words
caches use write-back, CP15 c7 for cache cleaning, and Format C for cache lockdown.

Table 3.8. Cache Type Register default values

Bits	Field	Value	Behavior
[31:29]	SBZ	b000	-
[28:25]	Ctype	b1110	-
[24]	S	b1	Harvard cache
[23:21]	SBZ	b000	-
[20:18]	Dsize	b101	16KB
[17:15]	Dassoc	b010	4-way
[14]	DM	b0	-
[13:12]	DLen	b10	8 words per line, 32 bytes
[11:9]	SBZ	b000	-
[8:6]	Isize	b101	16KB
[5:3]	Iassoc	b010	4-way
[2]	IM	b0	-
[1:0]	ILen	b10	8 words per line, 32 bytes

Table 3.9 shows the Cache Type Register default values for ARM1156T2F-S processor with 0KB cache size, and

separate instruction and data caches
0-way cache associativity
cache line length of eight words
caches use write-back, CP15 c7 for cache cleaning, and Format C for cache lockdown.

Table 3.9. Cache Type Register values for zero cache size

Bits	Field		Value	Behavior
[31:29]	Reserved		b000	-
[28:25]	Ctype		b1110	-
[24]	S		b1	Harvard cache
[23:21]	Dsize	Reserved	b000	-
[20:18]		Size	b000	0KB
[17:15]		Assoc	b000	0
[14]		M	b1	Cache absent
[13:12]		Len	b10	8 words per line, 32 bytes
[11:9]	Isize	Reserved	b000
[8:6]		Size	b000	0KB
[5:3]		Assoc	b000	0
[2]		M	b1	Cache absent
[1:0]		Len	b10	8 words per line, 32 bytes

Copyright © 2005-2007 ARM Limited. All rights reserved.	ARM DDI 0338G
Non-Confidential
PDF version