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This section includes some example sequences to illustrate how to transfer data between the DBGTAP debugger and the core when it is in Debug state. The examples are related to accessing the processor memory.
The DBGTAP debugger can use the following sequence for reading data from the processor memory system. The sequence assumes that the ARM register r0 contains a pointer to the address of memory at which the read has to start:
Scan_N into the IR.
1 into the SCREG.
INTEST into the IR.
Scan out the contents of the DSCR. This clears the sticky precise Data Abort and sticky imprecise Data Abort flags.
Scan_N into the IR.
4 into the SCREG.
EXTEST into the IR.
Scan in the LDC p14, c5, [R0], #4 instruction
into the ITR.
Scan_N into the IR.
5 into the SCREG.
INTEST into the IR.
Go through Run-Test/Idle state. The instruction loaded into the ITR is issued to the processor pipeline.
Scan out 34 bits of data. If the Ready flag is clear repeat this step again.
The instruction has completed execution. Store the least significant 32 bits.
Go to step 12 again for reading out more data.
Scan_N into the IR.
1 into the SCREG.
INTEST into the IR.
Scan out the contents of the DSCR. This clears the sticky precise Data Abort and sticky imprecise Data Abort flags. If the sticky precise Data Abort is set, this means that during the sequence one of the instructions caused a precise Data Abort. All the instructions that follow are not executed. Register r0 points to the next word to be read, and after the cause for the abort has been fixed the sequence resumes at step 5.
If the sticky imprecise Data Aborts flag is set, an imprecise Data Abort has occurred and the sequence restarts at step 1 after the cause of the abort is fixed and r0 is reloaded.
The DBGTAP debugger can use the following sequence for writing data to the processor memory system. The sequence assumes that the ARM register r0 contains a pointer to the address of memory at which the write has to start:
Scan_N into the IR.
1 into the SCREG.
INTEST into the IR.
Scan out the contents of the DSCR. This clears the sticky precise Data Abort and sticky imprecise Data Abort flags.
Scan_N into the IR.
4 into the SCREG.
EXTEST into the IR.
Scan in the STC p14, c5, [R0], #4 instruction
into the ITR.
Scan_N into the IR.
5 into the SCREG.
EXTEST into the IR.
Scan in 34 bits, the least significant 32 holding the word to be sent. At the same time, 34 bits are scanned out. If the Ready flag is clear, repeat this step.
Go through Run-Test/Idle state.
Go to step 12 again for writing in more data.
Scan in 34 bits. All the values are don’t care. At the same time, 34 bits are scanned out. If the Ready flag is clear, repeat this step. The don’t care value is written into the rDTR (Update-DR state) after Ready is seen set (Capture-DR state). However, the STC instruction is not re-issued because the DBGTAPSM does not go through Run-Test/Idle.
Scan_N into the IR.
1 into the SCREG.
INTEST into the IR.
Scan out the contents of the DSCR. This clears the sticky precise Data Abort and sticky imprecise Data Abort flags. If the sticky precise Data Abort is set, this means that during the sequence one of the instructions caused a precise Data Abort. All the instructions that follow are not executed. Register r0 points to the next word to be written, and after the cause for the abort has been fixed the sequences resumes at step 5.
If the sticky imprecise Data Abort flag is set, an imprecise Data Abort has occurred and the sequence restarts at step 1 after the cause of the abort is fixed and c0 is reloaded.
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0338G |
| Non-Confidential | |
| PDF version | |
| Home > Debug Test Access Port > Using the Debug Test Access Port > Example sequences |