Halting debug-mode is enabled by writing a 1 to bit 14 of the DSCR, see CP14 c1, Debug Status and Control Register (DSCR). This can only be done by a DBGTAP debugger hardware such as RealView ICE. When this mode is enabled the processor halts, instead of taking an exception in software, if one of the following events occurs:

The processor halts regardless of the state of bit 14 of the DSCR when:

The core halted bit in the DSCR is set when Debug state is entered. At this point, the debugger determines why the integer unit was halted and preserves the processor state. The MSR instruction can be used to change modes and gain access to all banked registers in the machine. While in Debug state:

Debug state is described in Debug state.