The DSCR[0] core halted bit is set.

The DBGACK signal is asserted, see External signals.

The DSCR[5:2] method of entry bits are set appropriately.

The CP15 IFSR, DFSR, and FAR registers are set as described in Effect of a debug event on CP15 registers. The WFAR is set to an Unpredictable value.

The processor is halted. The pipeline is flushed and no instructions are fetched.

The processor does not change the execution mode. The CPSR is not altered.

Interrupts and exceptions are treated as described in Interrupts and Exceptions.

Software debug events are ignored.

The external debug request signal is ignored.

Debug state entry request commands are ignored.

There is a mechanism, using the Debug Test Access Port, where the core is forced to execute an ARM state instruction. This mechanism is enabled using DSCR[13] execute ARM instruction enable bit.

The core executes the instruction as if it is in ARM state, regardless of the actual value of the T bit of the CPSR. If you do set both the J and T bits the behavior is Unpredictable.

In this state the core can execute any ARM state instruction, as if in a privileged mode. For example, if the processor is in User mode then the MSR instruction updates the PSRs and all the CP14 debug instructions can be executed. However, the processor still accesses the register bank and memory as indicated by the CPSR mode bits. For example, if the processor is in User mode then it sees the User mode register bank, and accesses the memory without any privilege.

In Debug state, the CP15 System Performance Monitor Registers do not count events. Therefore the debugger does not write events to the ETM. The Cycle Count Register, CCNT, stops counting in Debug state.

The PC behaves as described in Behavior of the PC in Debug state.

A DBGTAP debugger can force the processor out of Debug state by issuing a Restart instruction, see Table 14.1. The Restart command clears the DSCR[1] core restarted flag. When the processor has actually exited Debug state, the DSCR[1] core restarted bit is set and the DSCR[0] core halted bit and DBGACK signal are cleared.