17.13. RFE and SRS instructions
This section describes the cycle timing for the RFE and SRS instructions.
These instructions return from an exception and save exception
return state respectively. The RFE instruction always
requires two memory cycles. It first loads the SPSR value from the
stack, and then the return address. The SRS instruction
takes one or two memory cycles depending on doubleword alignment
first address location.
In all cases the base register is an Early register, and requires
an extra cycle of result latency to provide its value.
Table 17.20 shows
the cycle timing behavior for RFE and SRS instructions.
Table 17.20. RFE and SRS instructions cycle
timing behavior
| Example instruction | Cycles | Memory cycles |
|---|
| Address
doubleword aligned |
RFEIA <Rn>
| 10 | 2 |
SRSIA #<mode>
| 1 | 1 |
| Address
not doubleword aligned |
RFEIA <Rn>
| 10 | 2 |
SRSIA #<mode>
| 1 | 2 |
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