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The purpose of the memory region programming registers is to program the MPU regions.
There is one register that specifies which one of the 16 sets of region registers is to be accessed. Each region has its own register to specify:
region base address
region size and enable
region access control.
When the MPU is enabled:
the MPU determines the access permissions for all accesses to memory, which includes the TCM. Therefore, you must ensure that the memory regions in the MPU are programmed to cover the complete TCM address space with the appropriate access permissions. You must define at least one of the 16 regions in the MPU.
an access to an Undefined area of memory causes a background fault to be generated.
For the TCM space the processor uses the access permissions but ignores the region attributes from MPU.
The location of the TCM base address is set by CP15 c9. For more details, see c9, Data TCM Region Register.
The purpose of the Region Base Address is to describe the base address of a region. The region base address must always align to the region size.
The Region Base Address Register is:
in CP15 c6
a 32-bit read/write register
accessible in privileged modes only.
Figure 3.32 shows the arrangement of bits in the register.
Table 3.30 shows how the bit values correspond with the Region Base Address Register functions.
Table 3.30. Region Base Address Register bit functions
| Bits | Field | Function |
|---|---|---|
| [31:5] | Base address | Physical base address. Defines the base address of a region |
| [4:0] | SBZ | Should Be Zero |
To use the Data Region Base Address Register read or write CP15 with:
Opcode_1 set to 0
CRn set to c6
CRm set to c1
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c6, c1, 0 ;Read Data Region Base Address Register
MCR p15, 0, <Rd>, c6, c1, 0 ;Write Data Region Base Address Register
The purpose of the region size register is to:
hold the size of a region that is defined by the Memory Region Number Register
enable or disable the region defined by the Memory Region Number Register.
The Region Size and Enable Register is:
in CP15 c6
a 32-bit read/write register
accessible in privileged modes only.
Figure 3.33 shows the arrangement of bits in the register.
Table 3.31 shows how the bit values correspond with the Region Size Register functions.
To use the Region Size and Enable Register read or write CP15 with:
Opcode_1 set to 0
CRn set to c6
CRm set to c1
Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c6, c1, 2 ;Read Region Size and Enable Register
MCR p15, 0, <Rd>, c6, c1, 2 ;Write Region Size and Enable Register
Writing a region size that is outside the range results in Unpredictable behavior.
Table 3.31. Region Size Register bit functions
| Bits | Field | Function |
|---|---|---|
| [31:6] | SBZ | Should Be Zero |
| [5:1] | Region size | Region size. Defines the region size: b00000-b00011=Unpredictable b00100 = 32 bytes b00101 = 64 bytes b00110 = 128 bytes b00111 = 256 bytes b01000 = 512 bytes b01001 = 1KB b01010 = 2KB b01011 = 4KB b01100 = 8KB b01101 = 16KB b01110 = 32KB b01111 = 64KB b10000 = 128KB b10001 = 256KB b10010 = 512KB b10011 = 1MB b10100 = 2MB b10101 = 4MB b10110 = 8MB b10111 = 16MB b11000 = 32MB b11001 = 64MB b11010 = 128MB b11011 = 256MB b11100 = 512MB b11101 = 1GB b11110 = 2GB b11111 = 4GB |
[0] | En | Enable. Enables or disables a memory region: 0 = Memory region disabled. Memory regions are disabled on reset. 1 = Memory region enabled. A memory region must be enabled before it is used. |
The purpose of the Region Access Control Register is to hold the region attributes and access permissions for a given memory region.
The Region Access Control Register is:
in CP15 c6
a 32-bit read/write register
accessible in privileged modes only.
Figure 3.34 shows the arrangement of bits in the register.
Table 3.32 shows how the bit values correspond with the Region Access Control Register functions.
Table 3.32. Region Access Control Register bit functions
Bits | Field | Function |
|---|---|---|
[31:13] | Reserved. | |
| [12] | XN | Execute never. Determines if a region of memory is executable[1]: 0=All instruction fetches enabled 1=No instruction fetches enabled. |
| [11] | - | Reserved. |
| [10:8] | AP | Access permission. Defines the data access permissions.[2] For information on AP bit values, see Table 3.33. |
| [7:6] | - | Reserved. |
| [5:3] | TEX | Type extension. Defines the type extension attribute. [3] For information on TEX bit values, see Table 5.4. |
| [2] | S | Share. Determines if the memory region is Shared or Non-Shared: 0 = Non-Shared. If not present the S bit is assumed to be Non-Shared. 1 = Shared. This bit only applies to Normal, not Device or Strongly Ordered memory. |
| [1] | C | Cacheable. Determines if memory region type Cacheable: 0 = Non-Cacheable 1 = Cacheable. |
| [0] | B | Bufferable. Determines if memory region type Bufferable: 0 = Non-Bufferable 1 = Bufferable. |
[1] For more details, see Instruction access permissions. [2] For more details, see Data access permissions. [3] For more details, see Memory region attributes. | ||
Table 3.33 shows the AP bits values that determine the permissions for Privileged and User data access.
Table 3.33. Access data permission bit encoding
| AP bit values | Privileged permissions | User permissions | Description |
|---|---|---|---|
| b000 | No access | No access | All accesses generate a permission fault |
| b001 | Read/write | No access | Privileged access only |
| b010 | Read/write | Read-only | Writes in User mode generate permission faults |
| b011 | Read/write | Read/write | Full access |
| b100 | UNP | UNP | Reserved |
| b101 | Read-only | No access | Privileged read-only |
| b110 | Read-only | Read-only | Privileged/User read-only |
| b111 | UNP | UNP | Reserved |
To use the Region Access Control Registers read or write CP15 with:
Opcode_1 set to 0
CRn set to c6
CRm set to c1
Opcode_2 set to 4.
For example:
MRC p15, 0, <Rd>, c6, c1, 4;Read Region access control Register
MCR p15, 0, <Rd>, c6, c1, 4;Write Region access control Register
To execute instructions in User and/or Privileged mode:
the region must have read access as defined by the AP bits
the XN bit must be set to 0.
The memory region registers are multiple registers with one register for each memory region implemented. The value contained in the Memory Region Number Register determines which of the multiple registers is accessed.
The Memory Region Number Register is:
in CP15 c6
a 32-bit read/write register
accessible in privileged modes only.
Figure 3.35 shows the arrangement of bits in the register.
Table 3.34 shows how the bit values correspond with the Memory Region Number Register bits.
Table 3.34. Memory Region Number Register bit functions
| Bits | Field | Function |
|---|---|---|
| [31:4] | - | Reserved. |
| [3:0] | Region | Defines the group of registers to be accessed. The number of regions supported is defined by the MPU Type Register in the range b0000 - b1111. |
To use the Memory Region Number Registers read or write CP15 with:
Opcode_1 set to 0
CRn set to c6
CRm set to c1
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c6, c2, 0 ;Read Memory Region Number Register
MCR p15, 0, <Rd>, c6, c2, 0 ;Write Memory Region Number Register
Writing this register with a value of greater than or equal to the number of regions from the MPU Type Register, along with associated register bank accesses, are Unpredictable.
| Copyright © 2005-2007 ARM Limited. All rights reserved. | ARM DDI 0338G |
| Non-Confidential | |
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