ARM1156T2-S™ Technical Reference Manual 2.7.3. Execution state bits

2.7.3. Execution state bits

The execution state bits consist of the If-Then state bits, IT, Java state bit, J, and Thumb state bit, T.

IT state bits

The IT_cond field encodes the base condition code for the current IT block, if any. It must contain b000 when no IT block is active.

The a, b, c, d, and e bits encode the number of instructions that are to be conditionally executed, and whether the condition for each is the base condition code or the inverse of the base condition code. They must contain b00000 when no IT block is active.

When an IT instruction is executed, these bits are set according to the condition in the instruction, and the Then and Else (T and E) parameters in the instruction.

During execution of an IT block, the a, b, c, d, and e bits are shifted:

to reduce the number of instructions to be conditionally executed by one
to move the next bit into position to form the least significant bit of the condition code.

Table 2.2 shows how the IT execution state bits operate.

Table 2.2. Shifting of IT execution state bits

	Old state						New state
IT_cond	a	b	c	d	e	IT_cond	a	b	c	d	e
cond_base	P1	P2	P3	P4	1	cond_base	P2	P3	P4	1	0
cond_base	P1	P2	P3	1	0	cond_base	P2	P3	1	0	0
cond_base	P1	P2	1	0	0	cond_base	P2	1	0	0	0
cond_base	P1	1	0	0	0	b000	0	0	0	0	0

Table 2.3 shows the effect of each state.

Table 2.3. Effect of IT execution state bits

Entry point for:	IT_cond	a	b	c	d	e	Description
4-instruction IT block	cond_base	P1	P2	P3	P4	1	Next instruction has condition cond_base, P1
3-instruction IT block	cond_base	P1	P2	P3	1	0	Next instruction has condition cond_base, P1
2-instruction IT block	cond_base	P1	P2	1	0	0	Next instruction has condition cond_base, P1
1-instruction IT block	cond_base	P1	1	0	0	0	Next instruction has condition cond_base, P1
Invalid	non-zero	x	0	0	0	0	Unpredictable
Invalid	bxxx	1	0	0	0	0	Unpredictable
Not in an IT block	b000	0	0	0	0	0	Normal execution

Note

The IT state bits return as zero if an MRS of the CPSR is executed within an IT block in normal operation. In Debug state an MRS of the CPSR within an IT block return the IT state bits as shown in Table 2.2 and Table 2.3
Writing the IT bits by MSR instructions is ignored.

In Debug state an MRS of the CPSR within an IT block return the IT state bits as shown in Table 2.2 and Table 2.3.

For more details, see the ARM Architecture Reference Manual.

J bit

This bit is set to 0 on reset. For information on its behavior, see Acceleration of execution environments.

T bit

The T bit reflects the operating state:

when the T bit is set, the processor is executing in Thumb state
when the T bit is clear, the processor is executing in ARM state.

Note

Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If an MSR instruction does try to modify this bit the result is architecturally Unpredictable. In the ARM1156T2-S processor this bit is not affected.

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