The cache master valid bits are used to provide the ability to mask the valid bits held in the valid RAM for the cache. By doing this, a single cycle invalidation of the cache can be performed without requiring special resetable RAM cells. The number of master valid bits is a function of the cache size. There are 64 Cache master valid bits for a 16Kbyte cache, and the number of bits scales linearly with cache size. The maximum number of 32-bit registers required for the largest cache size (64K) is 8. The registers fill from the LSB of the lowest numbered register upwards with these valid bits.

Unimplemented valid bits are Unpredictable for reads and Should Be Zero or Preserved (SBZP) for writes.

Modifying the values of the valid bits using this mechanism can have Unpredictable effects. The intended usage is for these registers only to be written while the cache is disabled, and the values to be written are the values that were previously read out.

For the instructions that access the cache valid bits see c15, Instruction Cache Master Valid Register and c15, Data Cache Master Valid Register