ARM1156T2-S™ Technical Reference Manual 12.2. About the ARM1156T2-S VIC port

12.2. About the ARM1156T2-S VIC port

Figure 12.1 shows the VIC port and the Peripheral Interface connecting a PL192 VIC and an ARM1156T2-S processor.

Figure 12.1. Connection of a PL192 VIC to an ARM1156T2-S processor

The VIC port enables the processor to read the vector address as part of the IRQ interrupt entry. The ARM1156T2-S processor takes a vector address from this interface instead of using the pre-ARMv6 addresses, that is 0x00000018 or 0xFFFF0018.

The VIC port does not support the reading of FIQ vector addresses.

The interrupt interface is capable of managing interrupts asserted by a controller that clocks synchronously to the ARM1156T2-S processor clock. This ensures that the controller is used in systems that have a synchronous interface between the core clock and the AMBA clock.

The VIC port consists of the signals shown in Table 12.1.

Table 12.1. VIC port signals

Signal name	Direction	Description
nFIQ	Input	Active LOW fast interrupt request signal.
nIRQ	Input	Active LOW normal interrupt request signal.
INTSYNCEN	Input	If this signal is asserted, the internal nFIQ and nIRQ synchronizers are bypassed.
IRQADDRVSYNCEN	Input	If this signal is asserted, the internal IRQADDRV synchronizer is bypassed.
IRQACK	Output	Active HIGH IRQ acknowledge.
IRQADDRV	Input	Active HIGH valid signal for the IRQ interrupt vector address. Indicates when IRQADDR is valid
IRQADDR[31:2]	Input	IRQ interrupt vector address. IRQADDR[31:2] holds the address of the first ARM or Thumb instruction in the IRQ handler.

IRQACK is driven by the ARM1156T2-S processor to indicate to an external VIC that the processor wants to read the IRQADDR input.

IRQADDRV is driven by a VIC to tell the ARM1156T2-S processor that the address on the IRQADDR bus is valid and being held, and so it is safe for the processor to sample it.

IRQACK and IRQADDRV together implement a four-phase handshake between the ARM1156T2-S processor and a VIC. See Timing of the VIC port for more details.

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