This section describes the processor implementation of the AXI control signals:

For additional information about AXI, see the AMBA AXI Protocol Specification.

The AXI protocol is burst-based. Every transaction has address and control information on the address channel that describes the nature of the data to be transferred. The data is transferred between master and slave using a write channel to the slave or a read channel to the master. In write transactions, where all the data flows from the master to the slave, the AXI has an additional write response channel to enable the slave to signal to the master the completion of the write transaction.

The AXI protocol permits address information to be issued ahead of the actual data transfer and enables support for multiple outstanding transactions in addition to out-of-order completion of transactions.

Figure 8.2 shows how a read transaction uses the read address and read data channels.

Figure 8.3 shows how a write transaction uses the write address, write data, and write response channels.