Bits that are freely modifiable from any mode, either directly by MSR instructions or by other instructions whose side-effects include writing the specific bit or writing the entire CPSR.

Bits in Figure 2.5 that are in this category are N, Z, C, V, Q, GE[3:0], and E.

Bits that must never be modified by an MSR instruction, and so must only be written as a side-effect of another instruction. If an MSR instruction does try to modify these bits the results are architecturally Unpredictable. In the ARM1156T2-S processor these bits are not affected.

The bits in Figure 2.5 that are in this category are the execution state bits [24, 15:10, 5].

Bits that can only be modified from privileged modes, and that are completely protected from modification by instructions while the processor is in User mode. The only way that these bits can be modified while the processor is in User mode is by entering a processor exception, as described in Exceptions.

Bits in Figure 2.5 that are in this category are A, I, F, and M[4:0].