If the Data TCM and the data cache both contain the requested data address for a read, the ARM1156T2-S processor returns data from the Data TCM. For a write, the write occurs to the Data TCM. The majority of data accesses go to the data cache or to the Data TCM, but occasionally a data access reads or writes the Instruction TCM. Therefore this section describes data accesses to both TCMs.

The Instruction TCM base address is read by the ARM1156T2-S processor data port as a possible source for data for all memory accesses. This increases the address comparisons associated with the data, compared with the number required for the instruction memory lookup, for the level one memory hit generation. This functionality is required for reading literal values and for debug purposes, such as setting software breakpoints.

SWP and other memory synchronization operations, such as load-exclusive and store-exclusive, to instruction TCM are not supported, and result in Unpredictable behavior.

To save power, the processor predicts whether each data access needs to access the Data TCM. This prediction assumes that a data access will hit the Data TCM only if the previous data access hit the Data TCM. On an incorrect prediction the data access restarts, incurring a penalty of two or more cycles.

Access to the Instruction TCM involves a delay of at least three cycles in the reading or writing of the data. This delay means the Instruction TCM access can be scheduled to take place only when the presence of a hit to the Instruction TCM is known. This saves power and avoids unnecessary delays being inserted into the instruction-fetch side. This delay is applied to all accesses in a multiple operation in the case of an LDM, an LDCL, an STM, or an STCL.

The resulting behavior is architecturally Unpredictable if:

If an access is made to a location which is covered by both an Instruction TCM and a Data TCM, then access is to the Instruction TCM only.

It is not required for instruction port(s) to be able to access the Data TCM. An attempt to access addresses in the range covered by a Data TCM from an instruction port does not result in an access to the Data TCM. In this case, the instruction is fetched from main memory. It is anticipated that such accesses can result in external aborts in some systems, because the address range might not be supported in main memory.

Table 7.2 summarizes the results of data accesses to TCM and the cache. This also embodies the unexpected hit behavior for the cache described in Unexpected hit behavior.

The hit to the Data TCM and Instruction TCM refers to hitting an address in the range covered by that TCM.

Table 7.3 summarizes the results of instruction accesses to TCM and the cache. This also embodies the unexpected hit behavior for the cache described in Unexpected hit behavior. In Table 7.3, the instruction cache can only be hit if the memory location being accessed is marked as being Cacheable and not shareable. The hit to the Instruction TCM refers to hitting an address in the range covered by that TCM.