ARM1156T2-S™ Technical Reference ManualRevision: r0p4
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8.5.7. Noncacheable LDM4

The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for Noncacheable LDM4s addressing words 0 to 4 are shown in:

A Noncacheable LDM4 addressing words 5 to 7 is split into two operations as shown in Table 8.23.

Table 8.21. Noncacheable LDM4, Strongly Ordered or Device memory

Address[4:0]ARADDRRWARBURSTRWARSIZERWARLENRW
0x00, word 00x00Incr64-bit2 data transfers
0x04, word 10x04Incr32-bit4 data transfers
0x08, word 20x08Incr64-bit2 data transfers
0x0C, word 30x0CIncr32-bit4 data transfers
0x10, word 40x10Incr64-bit2 data transfers

Table 8.22. Noncacheable LDM4, Noncacheable memory or cache disabled

Address[4:0]ARADDRRWARBURSTRWARSIZERWARLENRW
0x00, word 00x00Incr64-bit2 data transfers
0x04, word 10x04Incr64-bit3 data transfers
0x08, word 20x08Incr64-bit2 data transfers
0x0C, word 30x0CIncr64-bit3 data transfers
0x10, word 40x10Incr64-bit2 data transfers

Table 8.23. Noncacheable LDM4 from word 5, 6, or 7

Address[4:0]Operations
0x14, word 5LDM3 from 0x14 + LDR from 0x00
0x18, word 6LDM2 from 0x18 + LDM2 from 0x00
0x1C, word 7LDR from 0x1C + LDM3 from 0x00
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