ARM1156T2-S™ Technical Reference ManualRevision: r0p4
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8.5.22. Cacheable Write-Through or Noncacheable STRB

Table 8.45 lists the values of AWADDRRW, AWBURSTRW, AWSIZERW, and AWLENRW for STRBs over the Data read/write interface.

Table 8.45. Cacheable Write-Through or Noncacheable STRB

Address[4:0]AWADDRRWAWBURSTRWAWSIZERWAWLENRWWSTRBRW
0x00, byte 00x00Incr8-bit1 data transferb0000 0001
0x01, byte 10x01Incr8-bit1 data transferb0000 0010
0x02, byte 20x02Incr8-bit1 data transferb0000 0100
0x03, byte 30x03Incr8-bit1 data transferb0000 1000
0x04, byte 40x04Incr8-bit1 data transferb0001 0000
0x05, byte 50x05Incr8-bit1 data transferb0010 0000
0x06, byte 60x06Incr8-bit1 data transferb0100 0000
0x07, byte 70x07Incr8-bit1 data transferb1000 0000
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