ARM1156T2-S™ Technical Reference Manual 8.5.34. Cacheable Write-Through or Noncacheable STM11

ARM1156T2-S™ Technical Reference Manual

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8.5.34. Cacheable Write-Through or Noncacheable `STM`11

An STM11 over the Data read/write interface is split into two or three operations as shown in Table 8.64.

Table 8.64. Cacheable Write-Through or Noncacheable STM11

Address[4:0]	Operations
`0x00`, word 0	`STM`8 to `0x00` + `STM`3 to `0x00`
`0x04`, word 1	`STM`7 to `0x04` + `STM`4 to `0x00`
`0x08`, word 2	`STM`6 to `0x08` + `STM`5 to `0x00`
`0x0C`, word 3	`STM`5 to `0x0C` + `STM`6 to `0x00`
`0x10`, word 4	`STM`4 to `0x10` + `STM`7 to `0x00`
`0x14`, word 5	`STM`3 to `0x14` + `STM`8 to `0x00`
`0x18`, word 6	`STM`2 to `0x18` + `STM`8 to `0x00` + `STR` to `0x00`
`0x1C`, word 7	`STR` to `0x1C` + `STM`8 to `0x00` + `STM`2 to `0x00`

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