Synchronizes IRQACK on its way in or bypasses the synchronizers if it is in synchronous mode.

Asserts IRQADDRV when an address is ready at IRQADDR, and holds that address until IRQACK is sampled LOW, even if higher priority interrupts come along.

Stacks the priority that corresponds to the vector address present at IRQADDR when it samples the IRQACK signal LOW (while IRQADDRV is HIGH).

Clears IRQADDRV so the processor can recognize another interrupt. If nIRQ is also to be deasserted at this point because there are no higher priority interrupts pending, it is deasserted before or at the same time as IRQADDRV to ensure that the processor does not take the same interrupt again.