Starts an interrupt entry sequence when it samples the nIRQ signal is LOW.

Determines if an FIQ or an IRQ is going to be taken. This happens after the interrupt entry sequence is started. If it decides that an IRQ is going to be taken, it starts the VIC port handshake by asserting IRQACK. If it decides that the interrupt is an FIQ, then it does not assert IRQACK and the VIC port handshake is not initiated.

Ignores the value of the nFIQ input until the IRQ interrupt entry sequence is completed if it has decided that the interrupt is an IRQ.

Samples the IRQADDR input bus when both IRQACK and IRQADDRV are sampled asserted. The interrupt entry sequence proceeds with this value of IRQADDR.

Ignores the nIRQ signal while IRQADDRV is HIGH. This gives the VIC time to deassert the nIRQ signal if there is no higher priority interrupt pending.

Ignores the nFIQ signal while IRQADDRV is HIGH.