ARM1156T2-S™ Technical Reference Manual 13.3.6. CP14 c7, Vector Catch Register (VCR)

13.3.6. CP14 c7, Vector Catch Register (VCR)

The ARM1156T2-S processor supports efficient exception vector catching. This is controlled by the VCR, as shown in Figure 13.5.

Figure 13.5. Vector Catch Register format

If one of the bits in this register is set and the corresponding vector is committed for execution, then a Debug exception or Debug state entry might be generated, depending on the value of the DSCR[15:14] bits (see Behavior of the processor on debug events). Under this model, any kind of fetch of an exception vector can trigger a vector catch, including the ones caused by exception entries.

The update of the VCR might occur several instructions after the corresponding MCR instruction. It only takes effect by the next Instruction Memory Barrier (IMB).

Table 13.6 shows the bitfield definitions for the Vector Catch Register.

Table 13.6. Vector Catch Register bitfield definitions

Bits	Normal address	High vector address	Description	Read/write attributes	Reset value
[31:8]	-	-	Reserved.	UNP/SBZP	-
[7] FIQ	`0x0000001C`	`0xFFFF001C`	Vector catch enable, FIQ	RW	0
[6] IRQ	Most recent^[1] IRQ address	Most recent^a IRQ address	Vector catch enable, IRQ	RW	0
[5]	-	-	Reserved	UNP/SBZP	-
[4] Data Abort	`0x00000010`	`0xFFFF0010`	Vector catch enable, Data Abort	RW	0
[3] Prefetch Abort	`0x0000000C`	`0xFFFF000C`	Vector catch enable, Prefetch Abort	RW	0
[2] SVC	`0x00000008`	`0xFFFF0008`	Vector catch enable, SVC	RW	0
[1] Undefined	`0x00000004`	`0xFFFF0004`	Vector catch enable, Undefined Instruction	RW	0
[0 Reset]	`0x00000000`	`0xFFFF0000`	Vector catch enable, Reset	RW	0
^[1]You can configure the ARM1156T2-S processor so that the IRQ uses vector exceptions other than `0x00000018` and `0xFFFF0018`. See Changes to existing interrupt vectors for more details.

Copyright © 2005-2007 ARM Limited. All rights reserved.	ARM DDI 0338G
Non-Confidential
PDF version