ARM1156T2-S ™ TechnicalReference Manual

Revision: r0p4


Table of Contents

Preface
About this manual
Product revision status
Intended audience
Using this manual
Conventions
Further reading
Feedback
Feedback on the product
Feedback on this manual
1. Introduction
1.1. About the ARM1156T2-S processor
1.2. ARM1156T2-S architecture with Thumb-2core technology
1.2.1. The Thumb-2 instruction set
1.3. Components of the processor
1.3.1. Core
1.3.2. Load Store Unit (LSU)
1.3.3. PreFetch Unit (PFU)
1.3.4. Level one memory system
1.3.5. AMBA AXI interface
1.3.6. Coprocessor interface
1.3.7. Debug
1.3.8. System control coprocessor
1.3.9. Interrupt handling
1.4. Power management
1.5. Configurable options
1.6. Pipeline stages
1.7. Typical pipeline operations
1.7.1. Instruction progression
1.8. About the architecture
1.9. Product revisions
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Processor operating states
2.2.1. Switching state
2.2.2. Interworking ARM and Thumb state
2.3. Operating modes
2.4. Data types
2.5. Memory formats
2.5.1. 32-bit word-invariant big-endian format
2.5.2. Little-endian format
2.6. Registers
2.6.1. The register set
2.7. The program status registers
2.7.1. The condition code flags
2.7.2. The Q flag
2.7.3. Execution state bits
2.7.4. Do Not Modify bits
2.7.5. The GE[3:0] bits
2.7.6. The E bit
2.7.7. The A bit
2.7.8. Interrupt disable bits
2.7.9. Mode bits
2.7.10. Reserved bits
2.7.11. Modification of PSR bits by MSR instructions
2.8. Exceptions
2.8.1. Changes to existing interrupt vectors
2.8.2. Instructions for exception handling
2.8.3. Exception entry and exit summary
2.8.4. Entering an exception
2.8.5. Leaving an exception
2.8.6. Reset
2.8.7. Fast interrupt request
2.8.8. Interrupt request
2.8.9. Low interrupt latency configuration
2.8.10. Interrupt latency example
2.8.11. Aborts
2.8.12. Imprecise Data Abort mask in the CPSR/SPSR
2.8.13. Supervisor Call instruction
2.8.14. Undefined instruction
2.8.15. Breakpoint instruction (BKPT)
2.8.16. Exception vectors
2.8.17. Exception priorities
2.9. Acceleration of execution environments
3. System Control Coprocessor
3.1. About control coprocessor CP15
3.1.1. System control processor functionalgroups
3.1.2. CP15 registers arranged by function
3.1.3. System control and configuration
3.1.4. MPU configuration and control
3.1.5. Cache configuration and control
3.1.6. TCM configuration and control
3.1.7. Cache debug and software test access
3.1.8. System performance monitor
3.2. System control processor registers
3.2.1. Use of the system control coprocessor
3.2.2. Register allocation
3.2.3. MCRR operations
3.2.4. c0, Main ID Register
3.2.5. c0, Cache Type Register
3.2.6. c0, TCM Status Register
3.2.7. c0, MPU Type Register
3.2.8. c0, Core feature ID registers
3.2.9. c1, Control Register
3.2.10. c1, Auxiliary ControlRegister
3.2.11. c1, CoprocessorAccess Control Register
3.2.12. c5, Data Fault StatusRegister
3.2.13. c5, Instruction FaultStatus Register
3.2.14. c6, Fault Address Register
3.2.15. c6, Watchpoint FaultAddress Register
3.2.16. c6, Instruction FaultAddress Register
3.2.17. c6, Memory region programmingregisters
3.2.18. c7, Cache OperationsRegister
3.2.19. c7, Cache Dirty StatusRegister
3.2.20. c9, Data and instructioncache lockdown registers
3.2.21. c9, Data TCM RegionRegister
3.2.22. c9, Instruction TCMRegion Register
3.2.23. c13, Process IDRegister
3.2.24. c15, Data CacheDebug Register
3.2.25. c15, Instruction CacheDebug Register
3.2.26. c15, Data cache TagRAM operation
3.2.27. c15, Tag RAM parityread operation
3.2.28. c15, Instruction cacheTag RAM operation
3.2.29. c15, Instruction CacheData RAM operation
3.2.30. c15, Cache Data RAMparity read operations
3.2.31. c15, Instruction CacheMaster Valid Register
3.2.32. c15, Data Cache MasterValid Register
3.2.33. c15, Cache Debug ControlRegister
3.2.34. c15, Data Cache ValidRAM and Dirty RAM bit write operation
3.2.35. c15, Performance MonitorControl Register
3.2.36. c15, Cycle CounterRegister
3.2.37. c15, Count Register0
3.2.38. c15, Count Register1
3.3. System control coprocessor referencedata
3.3.1. Instruction summary
4. Prefetch Unit
4.1. About the prefetch unit
4.2. Branch prediction
4.2.1. Enabling/disabling program flow prediction
4.2.2. Branch predictor
4.2.3. Branch folding
4.2.4. Incorrect predictions and correction
4.3. Return stack
4.4. Instruction Memory Barrier (IMB) instruction
4.4.1. Generic IMB use
4.4.2. ARM1020T or later IMB implementation
4.4.3. Execution of IMB instructions
5. Memory Protection Unit
5.1. About the MPU
5.1.1. Memory regions
5.1.2. Overlapping regions
5.1.3. Background regions
5.2. Enabling and disabling the MPU
5.2.1. Enabling the MPU
5.2.2. Disabling the MPU
5.3. Memory attributes and types
5.3.1. Normal memory attribute
5.3.2. Device memory attribute
5.3.3. Strongly Ordered memory attribute
5.3.4. Ordering requirements for memory accesses
5.3.5. Explicit memory barriers
5.3.6. Backwards compatibility
5.4. Memory region attributes
5.4.1. C and B bit, and type extension fieldencodings
5.4.2. Shared
5.5. Memory access control
5.5.1. Data access permissions
5.5.2. Instruction access permissions
5.6. MPU aborts
5.6.1. External aborts
5.7. Fault status and address
5.8. MPU fault checking
5.8.1. Fault checking sequence
5.8.2. Alignment fault
5.8.3. Background fault
5.8.4. Permission fault
5.9. Debug event
6. Unaligned and Mixed-Endian Data Access Support
6.1. About unaligned and mixed-endian support
6.2. Unaligned access support
6.2.1. Word-invariant mode support
6.2.2. ARMv6 extensions
6.2.3. Word-invariant mode and ARMv6 configurations
6.2.4. Word-invariant data access in ARMv6(U=0)
6.2.5. Support for unaligned data accessin ARMv6 (U=1)
6.2.6. ARMv6 unaligned data access restrictions
6.3. Unaligned data access specification
6.3.1. Load unsigned byte, endian independent
6.3.2. Load signed byte, endian independent
6.3.3. Store byte, endian independent
6.3.4. Load unsigned halfword, little-endian
6.3.5. Load unsigned halfword, big-endian
6.3.6. Load signed halfword, little-endian
6.3.7. Load signed halfword, big-endian
6.3.8. Store halfword, little-endian
6.3.9. Store halfword, big-endian
6.3.10. Load word, little-endian
6.3.11. Load word, big-endian
6.3.12. Store word, little-endian
6.3.13. Store word, big-endian
6.3.14. Load double, load multiple, load coprocessor (little-endian,E = 0)
6.3.15. Load double, load multiple, load coprocessor (big-endian,E=1)
6.3.16. Store double, store multiple, store coprocessor (little-endian,E=0)
6.3.17. Store double, store multiple, store coprocessor (big-endian,E=1)
6.4. Operation of unaligned accesses
6.5. Mixed-endian access support
6.5.1. Differences between BE-32 and BE-8 buses
6.5.2. Interaction between the Bus protocol and the coreendianness
6.5.3. Word-invariant fixed instruction anddata endianness
6.5.4. ARMv6 support for mixed-endian data
6.5.5. Reset values of the U, B, and EE bits
6.6. Instructions to reverse bytes in ageneral-purpose register
6.6.1. All load and store operations
6.7. Instructions to change the CPSR Ebit
7. Level One Memory System
7.1. About the level one memory system
7.2. Cache organization
7.2.1. Features of the cache system
7.2.2. Cache functional description
7.2.3. Cache control operations
7.2.4. Cache miss handling
7.2.5. Cache disabled behavior
7.2.6. Unexpected hit behavior
7.2.7. Cache parity errors
7.2.8. Cache associativity
7.3. Tightly-coupled memory
7.3.1. TCM behavior
7.3.2. Restriction on mappings
7.3.3. Restriction on attributes
7.3.4. TCM error detection signals
7.3.5. TCM accesses
7.4. TCM and cache interactions
7.4.1. Core access arbitration
7.4.2. Instruction accesses to TCM
7.4.3. Data accesses to TCMs
7.5. Peripheral port
7.6. Cache debug
7.7. Write Buffer
8. Level Two Interface
8.1. About the level two interface
8.1.1. Level two instruction-side controller
8.1.2. Level two data-side controller
8.2. Synchronization primitives
8.2.1. Load-exclusive instruction
8.2.2. Store-exclusive instruction
8.2.3. Example of LDREX and STREX usage
8.3. AXI control signals in the processor
8.3.1. Channel definition
8.3.2. Signal name suffixes
8.3.3. Address channel signals
8.4. Instruction fetch interface transfers
8.4.1. Cacheable fetches
8.4.2. Noncacheable fetches
8.5. Data read/write interface transfers
8.5.1. Linefills
8.5.2. Noncacheable LDRB
8.5.3. Noncacheable LDRH
8.5.4. Noncacheable LDR or LDM 1
8.5.5. Noncacheable LDRD or LDM 2
8.5.6. Noncacheable LDM 3
8.5.7. Noncacheable LDM 4
8.5.8. Noncacheable LDM 5
8.5.9. Noncacheable LDM 6
8.5.10. Noncacheable LDM 7
8.5.11. Noncacheable LDM 8
8.5.12. Noncacheable LDM 9
8.5.13. Noncacheable LDM 10
8.5.14. Noncacheable LDM 11
8.5.15. Noncacheable LDM 12
8.5.16. Noncacheable LDM 13
8.5.17. Noncacheable LDM 14
8.5.18. Noncacheable LDM 15
8.5.19. Noncacheable LDM 16
8.5.20. Half-line Write-Back
8.5.21. Full-line Write-Back
8.5.22. Cacheable Write-Through or Noncacheable STRB
8.5.23. Cacheable Write-Through or Noncacheable STRH
8.5.24. Cacheable Write-Through or Noncacheable STR or STM 1
8.5.25. Cacheable Write-Through or Noncacheable STRD or STM 2
8.5.26. Cacheable Write-Through or Noncacheable STM 3
8.5.27. Cacheable Write-Through or Noncacheable STM 4
8.5.28. Cacheable Write-Through or Noncacheable STM 5
8.5.29. Cacheable Write-Through or Noncacheable STM 6
8.5.30. Cacheable Write-Through or Noncacheable STM 7
8.5.31. Cacheable Write-Through or Noncacheable STM 8
8.5.32. Cacheable Write-Through or Noncacheable STM 9
8.5.33. Cacheable Write-Through or Noncacheable STM 10
8.5.34. Cacheable Write-Through or Noncacheable STM 11
8.5.35. Cacheable Write-Through or Noncacheable STM 12
8.5.36. Cacheable Write-Through or Noncacheable STM 13
8.5.37. Cacheable Write-Through or Noncacheable STM 14
8.5.38. Cacheable Write-Through or Noncacheable STM 15
8.5.39. Cacheable Write-Through or Noncacheable STM 16
8.6. Peripheral interface transfers
8.7. Endianness
8.8. Locked access
9. Clocking and Resets
9.1. ARM1156T2-S clocking
9.2. Reset
9.3. Reset modes
9.3.1. Power-on reset
9.3.2. Processor reset
9.3.3. DBGTAP reset
9.3.4. Normal operation
10. Power Control
10.1. About power control
10.2. Power management
10.2.1. Run mode
10.2.2. Standby mode
10.2.3. Shutdown mode
10.2.4. Dormant mode
10.2.5. Access to the cache valid bits
10.2.6. Communication to the Power Management Controller
11. Coprocessor Interface
11.1. About the coprocessor interface
11.2. Coprocessor pipeline
11.2.1. Coprocessor instructions
11.2.2. Coprocessor control
11.2.3. Pipeline synchronization
11.2.4. Pipeline control
11.2.5. Instruction tagging
11.2.6. Flush broadcast
11.3. Token queue management
11.3.1. Queue implementation
11.3.2. Queue modification
11.3.3. Queue flushing
11.4. Token queues
11.4.1. Instruction queue
11.4.2. Length queue
11.4.3. Accept queue
11.4.4. Cancel queue
11.4.5. Finish queue
11.5. Data transfer
11.5.1. Loads
11.5.2. Stores
11.6. Operations
11.6.1. Normal operation
11.6.2. Cancel operations
11.6.3. Bounce operations
11.6.4. Flush operations
11.6.5. Retirement operations
11.7. Multiple coprocessors
11.7.1. Interconnect considerations
11.7.2. Coprocessor selection
11.7.3. Coprocessor switching
12. Vectored Interrupt Controller Port
12.1. About the PL192 Vectored InterruptController
12.2. About the ARM1156T2-S VIC port
12.2.1. Synchronization of the VIC port signals
12.2.2. Interrupt handler exit
12.3. Timing of the VIC port
12.3.1. PL192 VIC timing
12.3.2. Core timing
12.4. Interrupt entry flowchart
13. Debug
13.1. Debug systems
13.1.1. The debug host
13.1.2. The protocol converter
13.1.3. The ARM1156T2-S processor
13.2. About the debug unit
13.2.1. Halting debug-mode debugging
13.2.2. Monitor debug-mode debugging
13.2.3. Programming the debug unit
13.3. Debug registers
13.3.1. Accessing debug registers
13.3.2. CP14 c0, Debug ID Register (DIDR)
13.3.3. CP14 c1, Debug Status and ControlRegister (DSCR)
13.3.4. CP14 c5, Data Transfer Registers (DTR)
13.3.5. CP14 c6, Watchpoint Fault Address Register (WFAR)
13.3.6. CP14 c7, Vector Catch Register (VCR)
13.3.7. CP14 c64-c69, Breakpoint Value Registers(BVR)
13.3.8. CP14 c80-c85, Breakpoint Control Registers(BCR)
13.3.9. CP14 c96-c97, Watchpoint Value Registers(WVR)
13.3.10. CP14 c112-c113, Watchpoint ControlRegisters (WCR)
13.4. CP14 registers reset
13.5. CP14 debug instructions
13.5.1. Executing CP14 debug instructions
13.6. Debug events
13.6.1. Software debug event
13.6.2. External debug request signal
13.6.3. Halt DBGTAP instruction
13.6.4. Behavior of the processor on debugevents
13.6.5. Behavior of the CPSR in Debug state
13.6.6. Effect of a debug event on CP15 registers
13.7. Debug exception
13.8. Debug state
13.8.1. Behavior of the PC in Debug state
13.8.2. Interrupts
13.8.3. Exceptions
13.8.4. Behavior on the execution state bits in Debug state
13.9. Debug communications channel
13.10. Debugging in a cached system
13.10.1. Data cache writes
13.11. Monitor debug-mode debugging
13.11.1. Entering the monitor target
13.11.2. Setting breakpoints, watchpoints,and vector catch debug events
13.11.3. Setting software breakpoint debugevents (BKPT)
13.11.4. Using the debug communications channel
13.12. Halting debug-mode debugging
13.12.1. Entering Debug state
13.12.2. Exiting Debug state
13.12.3. Programming debug events
13.13. External signals
14. Debug Test Access Port
14.1. Debug Test Access Port and Haltingdebug-mode
14.2. Synchronizing RealView™ ICE
14.3. Entering Debug state
14.4. Exiting Debug state
14.5. The DBGTAP port and debug registers
14.6. Debug registers
14.6.1. Bypass Register
14.6.2. Device ID Code Register
14.6.3. Instruction Register
14.6.4. Scan Chain Select Register (SCREG)
14.6.5. Scan chains
14.6.6. Reset
14.7. Using the Debug Test Access Port
14.7.1. Entering and leaving Debug state
14.7.2. Executing instructions in Debug state
14.7.3. Using the ITRsel IR instruction
14.7.4. Transferring data between the hostand the core
14.7.5. Using the debug communications channel
14.7.6. Target to host debug communicationschannel sequence
14.7.7. Host to target debug communicationschannel
14.7.8. Transferring data in Debug state
14.7.9. Example sequences
14.8. Debug sequences
14.8.1. Debug macros
14.8.2. General setup
14.8.3. Forcing the processor to halt
14.8.4. Entering Debug state
14.8.5. Leaving Debug state
14.8.6. Reading a current mode ARM registerin the range r0-r14
14.8.7. Writing a current mode ARM registerin the range r0-r14
14.8.8. Reading the CPSR/SPSR
14.8.9. Writing the CPSR/SPSR
14.8.10. Reading the PC
14.8.11. Writing the PC
14.8.12. General notes about reading and writing memory
14.8.13. Reading memory as words
14.8.14. Writing memory as words
14.8.15. Reading memory as halfwords or bytes
14.8.16. Writing memory as halfwords/bytes
14.8.17. Coprocessor register reads and writes
14.8.18. Reading coprocessor registers
14.8.19. Writing coprocessor registers
14.9. Programming debug events
14.9.1. Reading registers using scan chain7
14.9.2. Writing registers using scan chain7
14.9.3. Setting breakpoints, watchpoints andvector catches
14.9.4. Setting software breakpoints
14.10. Monitor debug-mode debugging
14.10.1. Receiving data from the core
14.10.2. Sending data to the core
15. Trace Interface Port
15.1. About the ETM interface
15.1.1. Instruction interface
15.1.2. Data address interface
15.1.3. Data value interface
15.1.4. Pipeline advance interface
15.1.5. Coprocessor interface
15.1.6. Other connections to the core
16. Test Features
16.1. About the test features
16.2. Memory BIST
16.2.1. Tag RAM access
16.2.2. ARM Memory BIST Controller
16.2.3. Third party tool support
16.3. Power-On Test
16.4. Running System Test
17. Cycle Timings and Interlock Behavior
17.1. About cycle timings and interlock behavior
17.1.1. Instruction execution overview
17.1.2. Conditional instructions
17.1.3. Opposite condition code checks
17.1.4. Definition of terms
17.1.5. Instruction sets
17.2. Register interlock examples
17.3. Data processing instructions
17.3.1. Cycle counts if destination is not PC
17.3.2. Cycle counts if destination is the PC
17.3.3. Example interlocks
17.4. QADD, QDADD, QSUB, and QDSUB instructions
17.5. ARMv6 media data-processing
17.6. ARMv6 Sum of Absolute Differences
17.6.1. Example interlocks
17.7. Multiplies
17.8. Branches
17.9. Processor state updating instructions
17.10. Single load and store instructions
17.10.1. Base register update
17.11. Load and Store Doubleword instructions
17.12. Load and Store Multiple instructions
17.12.1. Load and Store Multiples, other than Load Multiplesincluding the PC
17.12.2. Load Multiples, where the PC is in the register list
17.12.3. Example Interlocks
17.13. RFE and SRS instructions
17.14. Synchronization instructions
17.15. Coprocessor instructions
17.16. SVC, BKPT, undefined, and prefetchaborted instructions
17.17. CBZ, CBNZ, and IT instructions
17.18. Bitfield instructions
17.19. NOP (CPS) instruction
17.20. Table branch instructions
18. AC Characteristics
18.1. ARM1156T2-S timing diagrams
18.2. ARM1156T2-S timing parameters
18.2.1. Input port timing parameters
18.2.2. Output ports timing parameters
A. Processor Signal Descriptions
A.1. Global signals
A.2. Configuration signals
A.3. Interrupt signals (including VIC interfacesignals)
A.4. AXI interface signals
A.4.1. Instruction read port signals
A.4.2. Data port signals
A.4.3. Peripheral port signals
A.5. Instruction TCM Interface
A.6. Data TCM Interface
A.7. Coprocessor interface signals
A.8. Debug interface signals (includingJTAG)
A.9. ETM interface signals
A.10. Test signals
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. 32-bit ARM Thumb-2 instruction format
1.2. ARM1156T2-S processor block diagram
1.3. ARM1156T2-S pipeline stages
1.4. Typical operations in pipeline stages
1.5. Typical ALU operation
1.6. Typical multiply operation
1.7. Progression of an LDR/STR operation
1.8. Progression of an LDM/STM operation
1.9. Progression of an LDR that misses
2.1. Big-endian addresses of bytes withinwords
2.2. Little-endian addresses of byteswithin words
2.3. Register organization
2.4. ARM1156T2-S register set showingbanked registers
2.5. Program status register
3.1. System control and configurationregisters
3.2. MPU control and configuration registers
3.3. Cache control and configuration registers
3.4. TCM configuration and control registers
3.5. Cache debug and software test accessregisters
3.6. System performance monitor registers
3.7. CP15 ARM MRC and MCR bit pattern
3.8. CP15 ARM MRCC bit pattern
3.9. CP15 Thumb-2 MRC and MCR bit pattern
3.10. CP15 Thumb-2 MCRR bit pattern
3.11. Main ID Register format
3.12. Cache Type Register format
3.13. TCM Status Register format
3.14. MPU Type Register format
3.15. Processor Feature Register 0 format
3.16. Processor Feature Register 1 format
3.17. Debug Feature Register 0 format
3.18. Memory Model Feature Register 0 format
3.19. Memory Model Feature Register 1 format
3.20. Memory Model Feature Register 2 format
3.21. Memory Model Feature Register 3 format
3.22. Instruction Set Attributes Register0 format
3.23. Instruction Set Attributes Register1 format
3.24. Instruction Set Attributes Register2 format
3.25. Instruction Set Attributes Register3 format
3.26. Instruction Set Attributes Register4 format
3.27. Control Register format
3.28. Auxiliary Control Register format
3.29. Coprocessor Access Control Registerformat
3.30. DFSR format
3.31. IFSR format
3.32. Region Base Address Register format
3.33. Region Size Register
3.34. Region Access Control Register
3.35. Memory Region Number Register format
3.36. Cache operations registers
3.37. Cache Operation Register format forWay and Set
3.38. Cache Operation Register format forthe address
3.39. Cache Dirty Status Register format
3.40. Instruction and Data Cache LockdownRegisters format
3.41. Data TCM Region Register
3.42. Instruction TCM Region Register format
3.43. Format of the Process ID Register
3.44. Formats of the Data Cache Debug Register
3.45. Formats of the Instruction CacheDebug Register
3.46. Data Tag RAM read/write operationformat
3.47. Tag RAM parity read operation format
3.48. Instruction cache Tag RAM read/writeoperation format
3.49. Instruction Cache Data RAM read/writeoperation format
3.50. Cache Data RAM parity read operationformat
3.51. Cache Debug Control Register format
3.52. Data Cache Valid RAM and Dirty RAMbit write operation format
3.53. Performance Monitor Control Registerformat
5.1. MPU simplified block diagram
5.2. Overlapping memory regions
5.3. Overlay for stack protection
5.4. Memory map behavior for data andinstruction accesses when MPU is disabled
5.5. Fault checking sequence
6.1. Load unsigned byte
6.2. Load signed byte
6.3. Store byte
6.4. Load unsigned halfword, little-endian
6.5. Load unsigned halfword, big-endian
6.6. Load signed halfword, little-endian
6.7. Load signed halfword, big-endian
6.8. Store halfword, little-endian
6.9. Store halfword, big-endian
6.10. Load word, little-endian
6.11. Load word, big-endian
6.12. Store word, little-endian
6.13. Store word, big-endian
7.1. Level one cache block diagram
7.2. TCM read access
7.3. TCM write access
7.4. Error generation on read
7.5. Error correction on read
7.6. Stall cycles on read accesses
7.7. Stall cycles on write accesses
8.1. Level two interconnect interfaces
8.2. Channel architecture of reads
8.3. Channel architecture of writes
8.4. Swizzling of data and strobes inBE-32 big-endian configuration
9.1. Power-on reset
11.1. Core and coprocessor pipelines
11.2. Coprocessor pipeline and queues
11.3. Coprocessor pipeline
11.4. Token queue buffers
11.5. Queue reading and writing
11.6. Queue flushing
11.7. Instruction queue
11.8. Coprocessor data transfer
11.9. Instruction iteration for loads
11.10. Load data buffering
12.1. Connection of a PL192 VIC to an ARM1156T2-Sprocessor
12.2. VIC port timing example
12.3. Interrupt entry sequence
13.1. Typical debug system
13.2. Debug ID Register format
13.3. Debug Status And Control Registerformat
13.4. DTR format
13.5. Vector Catch Register format
13.6. Breakpoint Control Registers, format
13.7. Watchpoint Control Registers, format
14.1. JTAG DBGTAP state machine diagram
14.2. Clock synchronization
14.3. Bypass register bit order
14.4. Device ID code register bit order
14.5. Instruction register bit order
14.6. Scan chain select register bit order
14.7. Scan chain 0 bit order
14.8. Scan chain 1 bit order
14.9. Scan chain 4 bit order
14.10. Scan chain 5 bit order, EXTEST selected
14.11. Scan chain 5 bit order, INTEST selected
14.12. Scan chain 6 bit order
14.13. Scan chain 7 bit order
14.14. Behavior of the ITRsel IR instruction
15.1. ETMCPADDRESS format
16.1. Traditional method interfacing memoryBIST
16.2. Processor Memory BIST interface
16.3. Pipelining of the MBIST interface

List of Tables

1.1. Configurable options
2.1. Register mode identifiers
2.2. Shifting of IT execution state bits
2.3. Effect of IT execution state bits
2.4. GE[3:0] settings
2.5. PSR mode bit values
2.6. Exception entry and exit
2.7. Configuration of exception vector address locations
2.8. Exception vectors
2.9. Jazelle register instruction summary
3.1. CP15 register functions
3.2. Register allocation
3.3. MCRR operations
3.4. Main ID Register bit functions
3.5. Cache Type Register bit functions
3.6. Instruction and data cache sizes
3.7. Instruction and data cache associativity
3.8. Cache Type Register default values
3.9. Cache Type Register values for zero cache size
3.10. TCM Status Register bit functions
3.11. MPU Type Register bit functions
3.12. Processor Feature Register 0 bit functions
3.13. Processor Feature Register 1 bit functions
3.14. Debug Feature Register 0 bit functions
3.15. Memory Model Feature Register 0 bit functions
3.16. Memory Model Feature Register 1 bit functions
3.17. Memory Model Feature Register 2 bit functions
3.18. Memory Model Feature Register 3 bit functions
3.19. Instruction Set Attributes Register 0 bit functions
3.20. Instruction Set Attributes Register 1 bit functions
3.21. Instruction Set Attributes Register 2 bit functions
3.22. Instruction Set Attributes Register 3 bit functions
3.23. Instruction Set Attributes Register 4 bit functions
3.24. Control Register bit functions
3.25. Resultant B bit, U bit, and EE bit values
3.26. Auxiliary Control Register bit functions
3.27. Coprocessor Access Control Register bit functions
3.28. DFSR bit functions
3.29. IFSR bit functions
3.30. Region Base Address Register bit functions
3.31. Region Size Register bit functions
3.32. Region Access Control Register bit functions
3.33. Access data permission bit encoding
3.34. Memory Region Number Register bit functions
3.35. Cache Operations Register bit functions for Way and Set
3.36. Cache size and Way associativity
3.37. Cache size and S parameter dependency
3.38. Cache Operations Register bit functions for address
3.39. Cache Operations Register functions for single lines
3.40. Cache Operations Register functions for entire cache
3.41. Cache Operations Register Flush functions
3.42. Exception behavior to range operations
3.43. Cache Operations Register functions for address ranges
3.44. Results of access to the Data Memory Barrier operation
3.45. Instruction and Data Cache Lockdown Registers bit functions
3.46. Data TCM Region Register bit functions
3.47. Instruction TCM region register bit functions
3.48. Data Cache Debug Register bit arrangement after a Data TagRAMread/write operation
3.49. Data Cache Debug Register bit arrangement after a Data TagRAM parity read operation
3.50. Data Cache Debug Register bit arrangement after a Data CacheDataRAM parity read operation
3.51. Data Cache Debug Register bit arrangement after a Data Validand DirtyRAM write operation
3.52. Instruction Cache Debug Register bit arrangement after anInstruction cache Tag RAM read/write operation
3.53. Instruction Cache Debug Register bit arrangement after anInstructioncache Tag RAM parity read operation
3.54. Instruction Cache Debug Register bit arrangement after anInstructionCache Data RAM parity read operation
3.55. Data Tag RAM read/write operation bit functions
3.56. Data Tag RAM parity read operation bit functions
3.57. Instruction cache Tag RAM read/write operation bit functions
3.58. Instruction Cache Data RAM read/write operation bit functions
3.59. Cache Data RAM parity read operation bit functions
3.60. Cache Debug Control Register bit functions
3.61. Data Cache Valid RAM and Dirty RAM bit write operation bitfunctions
3.62. Performance Monitor Control Register bit functions
3.63. Performance monitoring events
3.64. Summary of CP15 instructions
5.1. Memory attributes
5.2. Memory ordering restrictions
5.3. Memory region backwards compatibility
5.4. TEX field, and C and B bit encodings used in Region AccessControl Registers
5.5. Cache policy bits
5.6. Inner and Outer cache policy implementation options
5.7. Access data permission bit encoding
5.8. Encodings for the fault status registers
5.9. Summary of aborts
6.1. Unaligned access handling
6.2. Access type descriptions
6.3. Alignment fault occurrence when access behavior is architecturallyunpredictable
6.4. Byte lanes used for LE, BE-8 and BE-32 accesses
6.5. Effect on E and B bits on instruction and data endianness
6.6. Word-invariant endianness using CP15 c1
6.7. Mixed-endian configuration
6.8. B bit, U bit, and EE bit settings
7.1. Effect of cache parity errors
7.2. Summary of data accesses to TCM and caches
7.3. Summary of instruction accesses to TCM and caches
8.1. AXI parameters for the level 2 interconnect interfaces
8.2. AxLEN[3:0] encoding
8.3. AxSIZE[2:0] encoding
8.4. AxBURST[1:0] encoding
8.5. AxLOCK[1:0] encoding
8.6. AxCACHE[3:0] encoding
8.7. AxPROT[2:0] encoding
8.8. AxSIDEBAND[4:1] encoding
8.9. ARSIDEBANDI[4:1] encoding
8.10. AXI signals for Cacheable fetches
8.11. AXI signals for Noncacheable fetches
8.12. Linefill behavior on the AXI interface
8.13. Noncacheable LDRB
8.14. Noncacheable LDRH
8.15. Noncacheable LDR or LDM 1
8.16. Noncacheable LDRD or LDM 2
8.17. Noncacheable LDRD or LDM 2 fromword 7
8.18. Noncacheable LDM 3, Strongly Ordered or Devicememory
8.19. Noncacheable LDM 3, Noncacheable memory or cachedisabled
8.20. Noncacheable LDM 3 from word 6, or 7
8.21. Noncacheable LDM 4, Strongly Ordered or Devicememory
8.22. Noncacheable LDM 4, Noncacheable memory or cachedisabled
8.23. Noncacheable LDM 4 from word 5, 6, or 7
8.24. Noncacheable LDM 5, Strongly Ordered or Devicememory
8.25. Noncacheable LDM 5, Noncacheable memory or cachedisabled
8.26. Noncacheable LDM 5 from word 4, 5, 6, or 7
8.27. Noncacheable LDM 6, Strongly Ordered or Devicememory
8.28. Noncacheable LDM 6, Noncacheable memory or cachedisabled
8.29. Noncacheable LDM 6 from word 3, 4, 5, 6, or 7
8.30. Noncacheable LDM 7, Strongly Ordered or Devicememory
8.31. Noncacheable LDM 7, Noncacheable memory or cachedisabled
8.32. Noncacheable LDM 7 from word 2, 3, 4, 5, 6, or7
8.33. Noncacheable LDM8 from word 0
8.34. Noncacheable LDM8 from word 1, 2, 3, 4, 5, 6, or 7
8.35. Noncacheable LDM9
8.36. Noncacheable LDM 10
8.37. Noncacheable LDM11
8.38. Noncacheable LDM12
8.39. Noncacheable LDM 13
8.40. Noncacheable LDM 14
8.41. Noncacheable LDM 15
8.42. Noncacheable LDM 16
8.43. Half-line Write-Back
8.44. Full-line Write-Back
8.45. Cacheable Write-Through or Noncacheable STRB
8.46. Cacheable Write-Through or Noncacheable STRH
8.47. Cacheable Write-Through or Noncacheable STR or STM 1
8.48. Cacheable Write-Through or Noncacheable STRD or STM 2 towords 0 to 6
8.49. Cacheable Write-Through or Noncacheable STRD or STM 2to word 7
8.50. Cacheable Write-Through or Noncacheable STM 3to words 0 to 5
8.51. Cacheable Write-Through or Noncacheable STM 3to words 6 or 7
8.52. Cacheable Write-Through or Noncacheable STM 4to word 0, 1, 2, 3, or 4
8.53. Cacheable Write-Through or Noncacheable STM 4to word 5, 6, or 7
8.54. Cacheable Write-Through or Noncacheable STM 5to word 0, 1, 2, or 3
8.55. Cacheable Write-Through or Noncacheable STM 5to word 4, 5, 6, or 7
8.56. Cacheable Write-Through or Noncacheable STM 6to word 0, 1, or 2
8.57. Cacheable Write-Through or Noncacheable STM 6to word 3, 4, 5, 6, or 7
8.58. Cacheable Write-Through or Noncacheable STM 7to word 0 or 1
8.59. Cacheable Write-Through or Noncacheable STM 7to words 2 to 7
8.60. Cacheable Write-Through or Noncacheable STM8 to word 0
8.61. Cacheable Write-Through or Noncacheable STM 8to words 1 to 7
8.62. Cacheable Write-Through or Noncacheable STM 9
8.63. Cacheable Write-Through or Noncacheable STM 10
8.64. Cacheable Write-Through or Noncacheable STM 11
8.65. Cacheable Write-Through or Noncacheable STM 12
8.66. Cacheable Write-Through or Noncacheable STM 13
8.67. Cacheable Write-Through or Noncacheable STM 14
8.68. Cacheable Write-Through or Noncacheable STM 15
8.69. Cacheable Write-Through or Noncacheable STM 16
8.70. Example Peripheral interface reads and writes
8.71. Endianness configuration
9.1. Reset modes
11.1. Coprocessor instructions
11.2. Coprocessor control signals
11.3. Pipeline stage update
11.4. Addressing of queue buffers
11.5. Retirement conditions
12.1. VIC port signals
13.1. Terms used in register descriptions
13.2. CP14 debug register map
13.3. Debug ID Register bitfield definition
13.4. Debug Status And Control Register bitfield definitions
13.5. Data Transfer Register bitfield definitions
13.6. Vector Catch Register bitfield definitions
13.7. ARM1156T2-S breakpoint and watchpoint registers
13.8. Breakpoint Value Registers, bitfield definition
13.9. Breakpoint Control Registers, bitfield definitions
13.10. Watchpoint Value Registers, bitfield definitions
13.11. Watchpoint Control Registers, bitfield definitions
13.12. CP14 debug instructions
13.13. Debug instruction execution
13.14. Behavior of the processor on debug events
13.15. Setting of CP15 registers on debug events
13.16. Values in the link register after exceptions
13.17. Read PC value after Debug state entry
14.1. Supported public instructions
14.2. Scan chain 7 register map
15.1. Instruction interface signals
15.2. ETMIACTL[17:0]
15.3. Data address interface signals
15.4. ETMDACTL[17:0]
15.5. Data value interface signals
15.6. ETMDDCTL[3:0]
15.7. ETMPADV[2:0]
15.8. Coprocessor interface signals
15.9. Other connections
16.1. Memory BIST interface ports
16.2. Instruction cache RAM access
16.3. Data bits for variable width instruction cache RAMs
16.4. Data cache RAM access
16.5. Data bits for variable width data cache RAMs
16.6. TCM RAM access
16.7. Data bits capability RAM blocks
17.1. Pipeline stages
17.2. Definition of cycle timing terms
17.3. Register interlock examples
17.4. Data processing instruction cycle timing behavior if destinationis not PC
17.5. Data processing instruction cycle timing behavior if destinationis the PC
17.6. QADD , QDADD , QSUB ,and QDSUB instruction cycle timing behavior
17.7. ARMv6 media data-processing instructions cycle timing behavior
17.8. ARMv6 SAD instruction timing behavior
17.9. Example interlocks
17.10. Example multiply instruction cycle timing behavior
17.11. Branch instruction cycle timing behavior
17.12. Processor state updating instructions cycle timing behavior
17.13. Cycle timing behavior for stores and loads, other than loadsto the PC
17.14. Cycle timing behavior for loads to the PC
17.15. <addr_md_1cycle> and <addr_md_2cycle> LDR example instruction explanation
17.16. Load and Store Doubleword instructions cycle timing behavior
17.17. <addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction explanation
17.18. Cycle timing behavior of Load and Store Multiples, otherthan load multiples including the PC
17.19. Cycle timing behavior of Load Multiples, where the PC isin the register list
17.20. RFE and SRS instructions cycletiming behavior
17.21. Synchronization instructions cycle timing behavior
17.22. Coprocessor instructions cycle timing behavior
17.23. SVC, BKPT, undefined, prefetch aborted instructions cycletiming behavior
17.24. CBZ and IT instructions cycle timing behavior
17.25. Thumb-2 bitfield instruction cycle timing behavior
17.26. Thumb-2 NOP (CPS) instruction cycle timing behavior
17.27. Thumb-2 table branch instructions cycle timing behavior
18.1. AXI bus interface input port timing parameters:
18.2. TCM interface port timing parameters
18.3. Coprocessor port timing parameters
18.4. ETM interface port timing parameters
18.5. Interrupt port timing parameters
18.6. Debug port timing parameters
18.7. Test port timing parameters
18.8. Static configuration signal port timing parameters
18.9. Output ports timing parameters
A.1. Global signals
A.2. Configuration signals
A.3. Interrupt Signals
A.4. Port signal name suffixes
A.5. Instruction read port AXI signal implementation
A.6. Data port AXI signal implementation
A.7. Peripheral port AXI signal implementation
A.8. Instruction TCM Interface signals
A.9. Data TCM Interface signals
A.10. Coprocessor interface signals
A.11. Debug interface signals
A.12. ETM interface signals
A.13. Test signals

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This document is intended only to assist the reader in theuse of the product. ARM Limited shall not be liable for any lossor damage arising from the use of any information in this document,or any error or omission in such information, or any incorrect useof the product.

Figure 14.1 reprintedwith permission from IEEE Std. 1149.1-2001, IEEE StandardTest Access Port and Boundary-Scan Architecture by IEEEStd. The IEEE disclaims any responsibility or liability resultingfrom the placement and use in the described manner.

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This document is Non-Confidential. The right to use, copyand disclose this document may be subject to license restrictionsin accordance with the terms of the agreement entered into by ARMand the party that ARM delivered this document to.

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Revision History
Revision A 10March 2005 First release for r0p0.
Revision B 10October 2005 Second release for r0p0. Enhancementto text.
Revision C 11October 2005 Third release for r0p0. Enhancementto figures.
Revision D 30June 2006 First release for R0p2.
Revision E 30June 2006 Second release for r0p2. Enhancementto text.
Revision F 31May 2007 First release for r0p4. Enhancement totext and Figures.
Revision G 31July 2007 Confidentiality changed to Non-Confidential.No change to contents.
Copyright ©  2005-2007 ARM Limited. All rights reserved. ARM DDI 0338G
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