Cortex™-A8 Technical Reference Manual 16.2.2. Data-processing instructions

Data-processing instructions are divided into the following subcatagories:

Data-processing instructions with a destination: AND, EOR, SUB, RSB, ADD, ADC, SBC, RCSC, ORR, BIC
Data-processing without a destination: TST, TEQ, CMP, CMN
Move instructions: MOV, MVN

The data-processing instruction tables exclude cases where the PC is the destination. Branch instructions describes these cases.

Table 16.1 shows the operation of data-processing instructions that use a destination.

Table 16.1. Data-processing instructions with a destination

Shift type	Cycles	Source1	Source2	Source3	Source4	Result1	Result2
Immediate	1	`Rn:E2`	`[Rd:E2]`	-	-	`Rd:E2`	-
Register	1	`Rn:E2`	`Rm:E2`	`[Rd:E2]`	-	`Rd:E2`	-
Shift by immediate, non-RRX	1	`Rn:E2`	`Rm:E1`	`[Rd:E2]`	-	`Rd:E2`	-
Shift by immediate, RRX^[1]	1	`Rn:E2`	`Rm:E1`	`[Rd:E2]`	-	`Rd:E2`	-
Shift by register	1	`Rn:E2`	`Rm:E1`	`Rs:E1`	`[Rd:E2]`	`Rd:E2`	-
^[1]One-cycle stall required before instruction execution.

Table 16.2 shows the operation of data-processing instructions that do not use a destination.

Table 16.2. Data-processing instructions without a destination

Shift type	Cycles	Source1	Source2	Source3	Source4	Result1	Result2
Immediate	1	`Rn:E2`	-	-	-	-	-
Register	1	`Rn:E2`	`Rm:E2`	-	-	-	-
Shift by immediate, non-RRX	1	`Rn:E2`	`Rm:E1`	-	-	-	-
Shift by immediate, RRX^[1]	1	`Rn:E2`	`Rm:E1`	-	-	-	-
Shift by register	1	`Rn:E2`	`Rm:E1`	`Rs:E1`	-	-	-
^[1]One-cycle stall required before instruction execution.

Table 16.3 shows the operation of MOV and MOVN instructions.

Table 16.3. MOV and MOVN instructions

Shift type	Cycles	Source1	Source2	Source3	Source4	Result1	Result2
Immediate^[1]	1	`[Rd:E2]`	-	-	`Rd:E1/E2`	-	-
Register^[1]	1	`Rn:E1`	`[Rd:E2]`	-	`Rd:E1/E2`	-	-
Shift by immediate, non-RRX^[1]	1	`Rn:E1`	`[Rd:E2]`	-	`Rd:E1/E2`	-	-
Shift by immediate, RRX^[2]	1	`Rn:E1`	`[Rd:E2]`	-	`Rd:E1/E2`	-	-
Shift by register	1	`Rn:E1`	`Rs:E1`	`[Rd:E2]`	`Rd:E1/E2`	-	-
^[1]Result is available in E2 if conditional. ^[2]Result is available in E2 if conditional. One-cycle stall required before instruction execution.

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