| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
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The processor has the following operating states controlled by the T bit and J bit in the CPSR.
32-bit, word-aligned ARM instructions are executed in this state.
T bit is 0 and J bit is 0.
16-bit and 32-bit, halfword-aligned Thumb-2 instructions.
T bit is 1 and J bit is 0.
16-bit and 32-bit, halfword-aligned variant of the Thumb-2 instruction set designed as a target for dynamically generated code. This is code compiled on the device either shortly before or during execution from a portable bytecode or other intermediate or native representation.
T bit is 1 and J bit is 1.
The processor does not support Jazelle state, that is, when the T bit is 0 and J bit is 1.
Transition between ARM and Thumb states does not affect the processor mode or the register contents. See ARM Architecture Reference Manual, Thumb-2 Execution Environment supplement for details on entering and exiting ThumbEE state.
| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Processor operating states |