Cortex™-A8 Technical Reference Manual 2.15.13. Exception priorities

2.15.13. Exception priorities

When multiple exceptions arise at the same time, a fixed priority system determines the order that they are handled. Table 2.13 shows the order of exception priorities.

Table 2.13. Exception priorities

Priority		Exception
Highest	1	Reset
	2	Precise data abort
	3	FIQ
	4	IRQ
	5	Prefetch abort
	6	Imprecise data abort
Lowest	7	BKPT Undefined Instruction SWI SMI

Some exceptions cannot occur together:

The BKPT, Undefined instruction, SMI, and SWI exceptions are mutually exclusive. Each corresponds to a particular, non-overlapping, decoding of the current instruction.
When FIQs are enabled, and a precise data abort occurs at the same time as an FIQ, the processor enters the Data Abort handler, and proceeds immediately to the FIQ vector.
A normal return from the FIQ causes the Data Abort handler to resume execution.
Precise data aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. You must add the time for this exception entry to the worst-case FIQ latency calculations in a system that uses aborts to support virtual memory.
The FIQ handler must not access any memory that can generate a data abort, because the initial Data Abort exception condition is lost if this happens.

Note

If the data abort is a precise external abort and bit [3] EA of SCR is set, the processor enters Monitor mode where aborts and FIQs are disabled automatically. Therefore the processor does not proceed to FIQ vector afterwards.

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