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When the processor is in integration mode, you can use the read/write Integration Internal Output Control Register to drive certain debug unit outputs to determine how they are connected to the Cross Triggered Interface (CTI).
Figure 12.19 shows the bit arrangement of the Integration Internal Output Control Register.
Table 12.34 shows how the bit values correspond with the Integration Internal Output Control Register functions.
Table 12.34. Integration Internal Output Control Register bit functions
| Bits | Field | Function |
|---|---|---|
[31:6] | - | RAZ for reads, SBZP for writes. |
| [5] | Internal DBGTRIGGER | Internal DBGTRIGGER. This bit drives the internal signal that goes from the debug unit to the CTI to indicate early entry to the debug state. The reset value is 0. |
[4] | Internal DBGRESTARTED | Internal DBGRESTARTED. This bit drives the internal signal that goes from the debug unit to the CTI to acknowledge success of a debug restart command. The reset value is 0. |
[3] | Internal nPMUIRQ | Internal nPMUIRQ. This bit drives the internal signal equivalent to nPMUIRQ that goes from the debug unit to the CTI. If this bit is set to 1, the corresponding internal nPMUIRQ signal is asserted, that is, cleared. The reset value is 0. |
[2] | Internal COMMTX | Internal COMMTX. This bit drives the internal signal equivalent to COMMTX that goes from the debug unit to the CTI. The reset value is 0. |
[1] | Internal COMMRX | Internal COMMRX. This bit drives the internal signal equivalent to COMMRX that goes from the debug unit to the CTI. The reset value is 0. |
[0] | Internal DBGACK | Internal DBGACK. This bit drives the internal signal equivalent to DBGACK that goes from the debug unit to the CTI. The reset value is 0. |
Both the DBGTRIGGER and DBGACK signals are asserted on entry to debug state. The only difference is that DBGTRIGGER is asserted before the implicit Data Synchronization Barrier (DSB) associated with the debug state entry, while DBGACK is asserted after the DSB.
| Copyright © 2006 ARM Limited. All rights reserved. | ARM DDI 0344B |
| Non-Confidential | |
| PDF version | |
| Home > Debug > Management registers > Integration Internal Output Control Register |