Cortex™-A8 Technical Reference Manual 3.2.3. c0, Cache Type Register

3.2.3. c0, Cache Type Register

The purpose of the Cache Type Register is to determine the instruction and data cache minimum line length in bytes to enable a range of addresses to be invalidated.

The Cache Type Register is:

a read-only register
accessible in privileged modes only.

The contents of the Cache Type Register depend on the specific implementation. Figure 3.2 shows the bit arrangement of the Cache Type Register.

Figure 3.2. Cache Type Register format

Table 3.6 shows how the bit values correspond with the Cache Type Register functions.

Table 3.6. Cache Type Register bit functions

Bits	Field	Function
[31:29]	-	Always read as 3'b100
[28:20]	-	Always read as 9'b000000000
[19:16]	DMinLine	Number of words of smallest line length in L1 or L2 data cache: 4'b0100 = sixteen 32-bit word data line length
[15:14]	L1 Ipolicy	VIPT instruction cache support: 2'b10 = virtual index, physical tag L1 Ipolicy
[13: 4]	-	Always read as 10'b0000000000
[3:0]	IMinLine	Number of words of smallest line length in L1 or L2 instruction cache: 4'b0100 = sixteen 32-bit word data line length

Table 3.7 shows the results of attempted access for each mode.

Table 3.7. Results of access to the Cache Type Register

Secure privileged		Nonsecure privileged		Secure User		Nonsecure User
Read	Write	Read	Write	Read	Write	Read	Write
Data	Undefined exception	Data	Undefined exception	Undefined exception	Undefined exception	Undefined exception	Undefined exception

To access the Cache Type Register, read CP15 with:

MRC p15, 0, <Rd>, c0, c0, 1 ; Read Cache Type Register

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